CODEWITHSUNDEEP
compiler-errorsvhdl
Răzvan Bălan
Răzvan Bălan

Reputation: 33

Can't manage to solve error ,VHDL, syntax error but I don't see it

I can't manage to solve the error in this multiplier. I am new in VHDL so it may be a very stupid question(I tried to fix the problem but it didn't seems like i've succeded) it says: Error: C:/modeltech_6.5/examples/pipe.vhd(41): near "label": syntax error

I am trying to make a pipeline multiplier for my project

entity  mult_secv  is 
  generic(
    Na    : integer := 8;
    Nb    : integer := 8;
    Nscnt : integer := 4
   );
  port(
    iCLK  : in std_logic;
    iRST    : in std_logic;
    iDV   : in std_logic;

    ia      : in std_logic_vector(Na-1 downto 0);
    ib      : in std_logic_vector(Nb-1 downto 0);

    oDV     : out std_logic;
    oDATA   : out std_logic_vector(Na+Nb-2 downto 0)
    );
end  mult_secv;

architecture produs of mult_secv is
  type my_array1 is array(1 to 8)of std_logic_vector(Na+Nb-2 downto 0);
  type my_array2 is array(1 to 8) of std_logic_vector(Nb-1 downto 0);
  type my_array3 is  array(1 to 8) of std_logic;
--8 stagii pentru a se calcula tot produsul
  signal sa, srez : my_array1;   
  signal sb : my_array2;
  signal dv : my_array3;
  constant scntmax : integer:=8 ;

begin
  -- for each pipeline stage
label : for scnt in 1 to scntmax generate ---> CAUTA SINTAXA PENTRU GENERARE DE COMPONENTE IDENTICE

process(iCLK,iRST)
begin
  if iRST= '1' then
    sa <= (others => (others => '0'));
  elsif rising_edge(iCLK) then
    -- first stage
    if (scnt = 1) then
      sa(scnt) <= (Na+Nb-2 downto Na => ia(Na-1))  & ia; ---se bordeaza cu bitul de semn daca e negativ
    -- other stages
    else
      sa(scnt) <= sa(scnt-1)(Na+Nb-3 downto 0) & '0';  --altfel se shifteaza sa
    end if;
  end if;
end process;


process(iCLK,iRST)
begin
  if iRST='1' then
    sb <= (others => (others => '0'));   
  elsif rising_edge(iCLK) then
    if (scnt = 1) then
      sb(scnt) <= ib;
    else
      sb(scnt) <= '0' & sb(scnt-1)(Nb-1 downto 1); --se shifteaza sb
    end if;
  end if;
end process;

process(iCLK,iRST)
begin
  if iRST='1' then
    srez <= (others => (others => '0'));  
  elsif rising_edge(iCLK) then
    if (scnt = 1) then
      if ib(Nb-1)='1' then
   srez(scnt) <= not (ia & (Nb-2 downto 0 => '0')) + '1'; --daca este negativ
      else
        srez(scnt) <= (others => '0'); --in primul stadiu
      end if;
    elsif sb(scnt-1)(0)='1' then        
      srez(scnt) <= srez(scnt-1)+sa(scnt-1);
    else    
      srez(scnt) <= srez(scnt-1);
    end if;
  end if;
end process;    

process(iCLK,iRST)
begin
  if iRST='1' then
    dv <= (others => '0');
  elsif rising_edge(iCLK) then
    if (scnt = 1) then
      dv(scnt) <= iDV;
    else
      dv(scnt) <= dv(scnt-1);
    end if;
  end if;
end process;

end generate label;

oDATA <= srez(scntmax);
oDv <= dv(scntmax);

end;

Can anyone help?

Upvotes: 0

Views: 2094

Answers (2)

user1818839
user1818839

Reputation:

ghdl reports:

ghdl -a mult_secv.vhd
mult_secv.vhd:31:1: unexpected token 'label' in a concurrent statement list
mult_secv.vhd:37:3: unexpected token 'elsif' in a concurrent statement list
mult_secv.vhd:42:5: unexpected token 'else' in a concurrent statement list
mult_secv.vhd:44:9: ';' is expected instead of 'if'
ghdl: compilation error

which makes it much clearer what the problem is.

I often find it useful to compile sources with more than one compiler; each has its own strengths and weaknesses.

Upvotes: 1

Paebbels
Paebbels

Reputation: 16249

label is a reserved keyword in VHDL. As you can see in your highlighted code above, it's blue :)

Upvotes: 0

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