CODEWITHSUNDEEP
syntaxcompiler-errorsvhdl
Josh
Josh

Reputation: 5

VHDL Syntax Error 10500

I am newer to this and this is homework but I am trying to understand this really inconsistent error. I have 2 errors; one at line 11 and one at line 17, they are both syntax errors

); -- line 11 BEGIN --line 17

Whole code

Library ieee;
Use ieee.std_logic_1164.all;
entity addsub4 is

port(
a: in std_logic_vector(3 downto 0);
b: in std_logic_vector (3 downto 0);
e: in std_logic;
carry: out std_logic;
over: out std_logic;
sout: out std_logic_vector (3 downto 0);
);
end addsub4;

architecture addsub4 of addsub4 is
signal c: std_logic_vector (4 downto 0);
signal bx: std_logic_vector (3 downto 0);
BEGIN
bx <= b xor e&e&e&e;
c(0) <= e;
s <= a xor bx xor c(3 downto 0);
c (4 downto 1) <= (a and bx) or (c(3 downto 0) and (a xor bx));
carry <= c(4);
over <= c(3) xor c(4);
end addsub4;

Upvotes: 0

Views: 2802

Answers (1)

Joachim Isaksson
Joachim Isaksson

Reputation: 180867

For the first error; in a PORT declaration, semicolon is a separator, not a terminator. In other words, the last declaration;

sout: out std_logic_vector (3 downto 0);

should just be

sout: out std_logic_vector (3 downto 0)

...since there's no further declaration to separate.

Upvotes: 2

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