CODEWITHSUNDEEP
verilog
Lerbi
Lerbi

Reputation: 225

How can you output a constant value in Verilog?

I am trying to output an array of 1280 bits, each 10 bits long, with the numbers 0->128.

I heard localparam may be the best option, but it seems like a strange request, so I'm wondering if anyone with experience may be able to help me.

Thanks

Upvotes: 1

Views: 2080

Answers (2)

dave_59
dave_59

Reputation: 42616

You can create a function that provides a constant value to a localparam or any other signal.

wire [1279:0] signal;

assign signal = pattern(0);

function [1279:0] pattern(input arg); // Verilog requires at least one argument to a function
integer i;
begin
     for (i=0;i<128;i=i+1)
       pattern[i*10 +:10] = i;
end
endfunction

SystemVerilog:

    wire [1279:0] signal;

    assign signal = pattern();

    function bit [1279:0] pattern(); 
      for (int i=0;i<128;i++)
           pattern[i*10 +:10] = i;
    endfunction

Upvotes: 1

Oldfart
Oldfart

Reputation: 6259

You can use a for-loop in an initial or reset statement:

reg [0:1279] big_vector;
integer i;

// here you need an initial
// or a reset section
   for (i=0; i<128; i=i+1)
      big_vector[ i*128 +: 10] = i;

If you do not touch/change big_vector the synthesis tool will convert it to a constant.

Upvotes: 1

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