CODEWITHSUNDEEP
verilog
Slater Victoroff
Slater Victoroff

Reputation: 21924

Using static values in Verilog

I am trying to make a simple mux in verilog from a decoder with an enable, but for some reason when I try to use the decoder within my mux with the enable locked to 1, I get an error. 

module DECODER(out1, out2, out3, out4, A, B, enable);

  `define NOT not #50
  `define AND and #50

  input A, B, enable;
  output out1, out2, out3, out4;
  wire notA, notB, val1, val2, val3, val4;

  `NOT first (notA, A);
  `NOT second (notB, B);

  `AND firstEval(val1, notA, notB);
  `AND secondEval(val2, notA, B);
  `AND thirdEval(val3, A, notB);
  `AND fourthEval(val4, A,B);

  `AND firstOutput(out1, val1, enable);
  `AND secondOutput(out2, val2, enable);
  `AND thirdOutput(out3, val3, enable);
  `AND fourthOutput(out4, val4, enable);
endmodule

module MUX (out, A, B, C, D, select1, select2);
  `define AND and #50
  `define OR or #50

  output out;
  input A,B,C,D,select1,select2;
  wire selectA, selectB, selectC, selectD, firstOr, secondOr, andA, andB, andC, andD;

  DECODER decoderModule(selectA, selectB, selectC, selectD, select1, select2,TRUE);

  `AND checkA(andA, selectA, A);
  `AND checkB(andB, selectB, B);
  `AND checkC(andC, selectC, C);
  `AND checkD(andD, selectD, D);

  `OR firstStep(firstOr, andA, andB);
  `OR secondStep(secondOr, firstOr, andC);

  `OR throughPut(out, secondOr, selectD);

endmodule

module TEST;
  reg A,B,C,D, select1, select2;
  wire out;

  initial
  begin
    A = 1; B = 1; C = 1; D = 1; select1 = 0; select2 = 0;
    #300 A = 0;
    #300 A = 1;
    #300 select1 = 1;
    #300 B = 0;
    #300 B = 1;
    #300 select2 = 1;
    #300 D = 0;
    #300 D = 1;
    #300 select1 = 0;
    #300 C = 0;
    #300 C = 1;
  end

  MUX UUT(out, A,B,C,D,select1,select2);

  initial
    $monitor($time, ,out, , A,B,C,D,select1,select2);
endmodule

When I run the simulation I get the following error:

# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.1c/win32pe_edu/Mux.v(9): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'enable'. The port definition is at: C:/Modeltech_pe_edu_10.1c/win32pe_edu/Decoder.v(1).

Any help on how to fix this would be greatly appreciated. I feel like I may be misunderstanding something about how Verilog uses static values.

Upvotes: 2

Views: 2193

Answers (2)

user597225
user597225

Reputation:

In your code, TRUE looks like an implicit wire declaration but I'm not sure why Modelsim thinks it is 32 bits. You can prevent these with a preprocessor directive.

`default_nettype none

Also, you should consider using parameters for constants since they are limited in scope.

parameter TRUE = 1'b1;

Upvotes: 2

toolic
toolic

Reputation: 62236

You have not provided a definition of the TRUE signal. I have replaced your TRUE with 1'b1 and now the simulation runs better:

  DECODER decoderModule(selectA, selectB, selectC, selectD, select1, select2, 1'b1);

Undeclared signals default to 1'bx in most simulators.

Alternately, you could declare TRUE as a wire in your MUX moodule:

wire TRUE = 1'b1;

Upvotes: 3

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