CODEWITHSUNDEEP
verilogsystem-veriloguvm
newbie
newbie

Reputation: 4809

Using Systemverilog static variable in class

I'm stuck in a problem and would appreciate any input/suggestion:

I've an agent for my test bench which has following components: a base class A- it defines two static variables- X and Y two new classes B and C, BOTH extended from A. They both use the static variable declared in base class. Another class D which utilizes B and C to do something.

Lets say class D is my top agent and I call it bfm_agent. This bfm_agent can be instantiated multiple times in my test bench. Now the problem is, X and Y will be shared to all bfm_agent. I don't want that. I just want X and Y to be static so that class B and C inside each bfm_agent can use these two variables to do some work.

How can I achieve this? I just want the scope of these two static variable to be valid only within each instance of bfm_agent.

Upvotes: 0

Views: 2722

Answers (1)

dave_59
dave_59

Reputation: 42788

You should use a configuration object that contains the variables X and Y. Then have the base class A construct the config object if it does not exist and then do set it for each instance of the agent. 

class A extends uvm_component;

my_config_c myconfig;

function void build_phase(uvm_phase phase);
...
  if(!uvm_config_db#(myconfig)::get(get_parent(),"","myconfig",myconfig)) begin
     myconfig = my_config_c::type_id::create("myconfig");
     uvm_config_db#(myconfig)::set(get_parent(),"","myconfig",myconfig)
  end
endfunction

Now both classes B and C will be able to refer to myconfig.X and myconfig.Y.

Upvotes: 2

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