StackOverflow Questions for Tag: uvm

omar sweiss

Reputation: 1

Interface port must be passed an actual interface error

verilogsystem-verilogverificationuvmquestasim

Score: -1

Answers: 0

Dev Munvar

Reputation: 13

Why does APB testbench not send data into the prdata register?

verilogsystem-veriloguvmtest-benchedaplayground

Score: 1

Answers: 1

sunbelt

Reputation: 71

How to print topology in UVM?

system-veriloguvm

Score: 1

Answers: 1

Sarth Rana

Reputation: 11

`define value assignment to a string

verilogsystem-verilogverificationuvm

Score: 0

Answers: 1

gyuunyuu

Reputation: 694

Does SystemVerilog have a log package that allows fine control over log messages?

system-veriloguvm

Score: 1

Answers: 1

Harsha Vardhan Kaki

Reputation: 11

ERROR VCP2000 "Syntax error. Unexpected token: initial." "testbench.sv" 50 7

syntax-errorsystem-veriloguvmvlsi

Score: 1

Answers: 1

greeting

Reputation: 15

what is the purpose of UVM automation macro?

uvm

Score: -1

Answers: 1

noobuntu

Reputation: 913

One IMP_PORT connected to multiple EXPORTS

system-veriloguvm

Score: 0

Answers: 1

Szt13

Reputation: 21

In UVM can we override base_test with base1_test ? with everything else remaining same?

system-veriloguvm

Score: 2

Answers: 1

Gautam

Reputation: 375

Can there be two 'uvm_tlm_b_target_socket' and two corresponding 'b_transport' implementation in a single object?

uvm

Score: 0

Answers: 2

BforB

Reputation: 19

UVM testbench for APB driver run_phase logic

verilogsystem-veriloguvmvlsiamba

Score: 1

Answers: 1

herbert.x

Reputation: 1

how to use macro with an argument in the `uvm_object_utils

macrosverilogsystem-veriloguvm

Score: 0

Answers: 1

Alok

Reputation: 31

How to randomize a variable in system verilog only if it's not having a default value

constraintssystem-veriloguvm

Score: 1

Answers: 2

G. B.

Reputation: 628

UVM enforce clocking block usage

system-verilogverificationuvm

Score: 0

Answers: 1

Boa

Reputation: 1

Regarding Configdb set and get issues in UVM

system-veriloguvm

Score: -2

Answers: 1

nguthrie

Reputation: 2685

UVM: illegal combination of driver and procedural assignment warning

system-veriloguvm

Score: 4

Answers: 1

Awang

Reputation: 1

Is it better to use uvm_reg_file for an array of uvm_reg objects or just declare an array in a uvm_reg_block?

uvm

Score: 0

Answers: 1

user1978273

Reputation: 514

uvm configure_phase is never called

system-veriloguvm

Score: -1

Answers: 1

G. B.

Reputation: 628

UVM agents - single/multiple?

architectureverificationuvm

Score: 1

Answers: 1

newbie99

Reputation: 51

UVM RAL: NULL pointer is dereference

verilogsystem-verilogverificationuvm

Score: -1

Answers: 1

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StackOverflow Questions for Tag: uvm

Interface port must be passed an actual interface error

Why does APB testbench not send data into the prdata register?

How to print topology in UVM?

`define value assignment to a string

Does SystemVerilog have a log package that allows fine control over log messages?

ERROR VCP2000 &quot;Syntax error. Unexpected token: initial.&quot; &quot;testbench.sv&quot; 50 7

what is the purpose of UVM automation macro?

One IMP_PORT connected to multiple EXPORTS

In UVM can we override base_test with base1_test ? with everything else remaining same?

Can there be two &#39;uvm_tlm_b_target_socket&#39; and two corresponding &#39;b_transport&#39; implementation in a single object?

UVM testbench for APB driver run_phase logic

how to use macro with an argument in the `uvm_object_utils

How to randomize a variable in system verilog only if it&#39;s not having a default value

UVM enforce clocking block usage

Regarding Configdb set and get issues in UVM

UVM: illegal combination of driver and procedural assignment warning

Is it better to use uvm_reg_file for an array of uvm_reg objects or just declare an array in a uvm_reg_block?

uvm configure_phase is never called

UVM agents - single/multiple?

UVM RAL: NULL pointer is dereference

ERROR VCP2000 "Syntax error. Unexpected token: initial." "testbench.sv" 50 7

Can there be two 'uvm_tlm_b_target_socket' and two corresponding 'b_transport' implementation in a single object?

How to randomize a variable in system verilog only if it's not having a default value