StackOverflow Questions for Tag: uvm

Rutuja14

Reputation: 7

Conditional creation of covergroup

system-veriloguvm

Score: -1

Answers: 1

Stepan Harutyunyan

Reputation: 17

Can you connect multiple analysis ports to single implementation?

system-verilogverificationuvm

Score: 1

Answers: 2

noobuntu

Reputation: 913

print_config does not display values

system-veriloguvm

Score: 0

Answers: 1

shailesh tripathi

Reputation: 66

Virtual interface between monitor/driver and their BFM ??? What they are actually, can someone explain?

system-veriloguvm

Score: 0

Answers: 2

thorondor1990

Reputation: 81

Structure containing dynamic data in non-procedural context for parameterized test class

system-veriloguvm

Score: 1

Answers: 1

Melandru's Square

Reputation: 454

Can you use uvm_reg.get() on a volatile reg?

system-veriloguvm

Score: 1

Answers: 1

Alexandr Bolotnikov

Reputation: 35

regexp in hdl path for UVM hdl access functions

system-veriloguvmsystem-verilog-dpi

Score: 1

Answers: 1

Grace90

Reputation: 227

Mirrored value doesn't match the desired value while running default sequence uvm_reg_hw_reset_seq in ral test

system-veriloguvm

Score: 0

Answers: 0

Swathi Bardhabad

Reputation: 1

An abstract class cannot be instantiated in module

classmodulesystem-verilognew-operatoruvm

Score: -1

Answers: 1

이정한

Reputation: 1

Unexpected Queue Randomization with UVM environment

oopverilogsystem-veriloguvm

Score: -2

Answers: 1

MoniCa

Reputation: 71

How to get property of class handle after override in UVM?

system-veriloguvm

Score: 2

Answers: 1

Siraj Mubarak

Reputation: 1

Is it possible to create a uvm-test dynamically from a string pased via UVM_TESTNAME but then override the base-test with the newly crearted test?

command-line-interfacesystem-veriloguvm

Score: -1

Answers: 1

robin tamrakar

Reputation: 1

Is there any way to convert hierarchy as string to actual hierarchy

system-veriloguvm

Score: 0

Answers: 3

Grace90

Reputation: 227

Constraint for square sub matrices in a matrix

matrixconstraintssystem-veriloguvm

Score: -1

Answers: 2

Grace90

Reputation: 227

I am trying to understand the way I can write a UVM scoreboard for a DUT (arbiter) with multiple masters and one slave

system-verilogverificationuvmamba

Score: 1

Answers: 1

Grace90

Reputation: 227

Multi-master AXI interface connections

system-veriloguvmtest-benchamba

Score: 1

Answers: 1

Leo

Reputation: 97

Why uvm_hdl_force has effect only in interactive mode in Verdi?

system-veriloguvm

Score: 0

Answers: 1

benjstark

Reputation: 95

If a single test case can not make the functional coverage get nearly 100%, is it acceptable to use several test cases to hit every point?

system-verilogverificationuvmfunction-coverage

Score: 1

Answers: 2

Grace90

Reputation: 227

How to write UVM driver and sequence item for a vending machine design (interview question)?

system-verilogverificationuvm

Score: 1

Answers: 1

AnuragChauhan

Reputation: 163

Why uvm_driver class is not abstract class while other like class uvm_sequence also parameterized class but it is abstract one?

system-veriloguvm

Score: -2

Answers: 2

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StackOverflow Questions for Tag: uvm

Conditional creation of covergroup

Can you connect multiple analysis ports to single implementation?

print_config does not display values

Virtual interface between monitor/driver and their BFM ??? What they are actually, can someone explain?

Structure containing dynamic data in non-procedural context for parameterized test class

Can you use uvm_reg.get() on a volatile reg?

regexp in hdl path for UVM hdl access functions

Mirrored value doesn&#39;t match the desired value while running default sequence uvm_reg_hw_reset_seq in ral test

An abstract class cannot be instantiated in module

Unexpected Queue Randomization with UVM environment

How to get property of class handle after override in UVM?

Is it possible to create a uvm-test dynamically from a string pased via UVM_TESTNAME but then override the base-test with the newly crearted test?

Is there any way to convert hierarchy as string to actual hierarchy

Constraint for square sub matrices in a matrix

I am trying to understand the way I can write a UVM scoreboard for a DUT (arbiter) with multiple masters and one slave

Multi-master AXI interface connections

Why uvm_hdl_force has effect only in interactive mode in Verdi?

If a single test case can not make the functional coverage get nearly 100%, is it acceptable to use several test cases to hit every point?

How to write UVM driver and sequence item for a vending machine design (interview question)?

Why uvm_driver class is not abstract class while other like class uvm_sequence also parameterized class but it is abstract one?

Mirrored value doesn't match the desired value while running default sequence uvm_reg_hw_reset_seq in ral test