CODEWITHSUNDEEP
verilog
joe
joe

Reputation: 533

I cannot assign output to value in Verilog

I am trying to assign ADDR to pcOut but ADDR is showing up as xxxxxxxx in GTKWave.

Here is my code:

module processor (
    input CLK,

    // Memory
    input [31:0] DATAOUT, // Memory data out
    output [31:0] DATAIN, // Memory data in
    output [31:0] ADDR, // Memory address
    output WE // Memory write enable
);
    wire [3:0] aluSel;
    wire [4:0] regSel1, regSel2, regDataSel;
    wire regLoad, aluEnable, pcLoad, pcNext;
    wire [31:0] regDataIn, regDataOut1, regDataOut2, aluOut, pcOut, pcIn, aluA, aluB;

    assign ADDR = pcOut;

    controlUnit controlUnit (
        .CLK(CLK), // Clock

        // Outputs
        .memDataOut(DATAOUT),
        .regDataOut1(regDataOut1),
        .regDataOut2(regDataOut2),
        .aluOut(aluOut),
        .pcOut(pcOut),

        // Load and enable
        .pcLoad(pcLoad),
        .regLoad(regLoad),
        .aluEnable(aluEnable),

        .pcNext(pcNext),

        // Selects
        .aluSel(aluSel),
        .regSel1(regSel1),
        .regSel2(regSel2),
        .regDataSel(regDataSel),

        // Inputs
        .pcIn(pcIn),
        .regDataIn(regDataIn),
        .aluA(aluA),
        .aluB(aluB),
        .memDataIn(DATAIN),
        .memAddr(ADDR)
    );

    datapath datapath (
        .pcNext(pcNext),

        // Load and enable
        .pcLoad(pcLoad),
        .regLoad(regLoad),
        .aluEnable(aluEnable),

        // Selects
        .aluSel(aluSel),
        .regSel1(regSel1),
        .regSel2(regSel2),
        .regDataSel(regDataSel),

        // Inputs
        .regDataIn(regDataIn),
        .pcIn(pcIn),
        .aluA(aluA),
        .aluB(aluB),

        // Outputs
        .regDataOut1(regDataOut1),
        .regDataOut2(regDataOut2),
        .aluOut(aluOut),
        .pcOut(pcOut)
    );
endmodule

Can anyone help? Thanks in advance.

Edit: pcOut is outputting the correct value but ADDR is not being set that same value.

Edit 2: Here is the code for the controlUnit module:

module controlUnit (
    input CLK,
    input [31:0] memDataOut, regDataOut1, regDataOut2, aluOut, pcOut,
    output reg [0:0] pcLoad, regLoad, aluEnable, pcNext,
    output reg [3:0] aluSel,
    output reg [4:0] regSel1, regSel2, regDataSel,
    output reg [31:0] pcIn, regDataIn, aluA, aluB, memDataIn, memAddr
);
    reg cycle = 0;
    wire [10:0] opcode;
    wire [4:0] rs1, rs2, rd;

    decoder decoder (
        .cycle(cycle),
        .instruction(memDataOut),

        .rs1(rs1),
        .rs2(rs2),
        .rd(rd),
        .opcode(opcode)
    );

    always @(posedge CLK) begin
        case (cycle)
            1'b0: begin
                regLoad <= 0;
                aluEnable <= 0;
                pcNext <= 0;
            end
            1'b1: begin
                pcNext <= 1;
                case (opcode)
                    11'b00000110011: begin // Add
                        regSel1 <= rs1;
                        regSel2 <= rs2;
                        regDataSel <= rd;
                        aluSel <= 0;
                        aluEnable <= 1;
                        regDataIn <= aluOut;
                        regLoad <= 1;
                    end
                    11'b10000110011: begin // Sub
                    end
                endcase
            end
        endcase

        cycle <= !cycle;
    end
endmodule

Upvotes: 0

Views: 298

Answers (1)

Kevin Kruse
Kevin Kruse

Reputation: 269

Your controlUnit doesn't seem to have any logic attached to memAddr, but memAddr is still an output of controlUnit. At the top level, you port map ADDR to .memAddr, and you also assign ADDR = pcOut. You're trying to drive ADDR in two different locations.

Upvotes: 2

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