CODEWITHSUNDEEP
verilog
Luis Hernandez
Luis Hernandez

Reputation: 5

My Verilog output test results in a value of x

This is my first assignment with Verilog and I cant figure out why my output keeps giving me x value, my code is very simple, I doubt it needs very much explanation.

module Network_Router (P, Q, R, S, Output);
input P, Q, R, S; 
output Output;
wire Output;
reg and1, and2, and3, and4, and5, and6, or1, or2, or3, or4, or5;
initial
begin
and1 = P & Q;
and2 = Q & R;
or1 = and1 | and2;

and3 = P & R;
and4 = S & R;
or2 = and3 | and4;

or3 = or1 | or2;

and5 = Q & S;
and6 = P & S;
or4 = and5 | and6;
or5 = or3 | or4;
end
assign Output = or5;
endmodule

and then my testbench filelooks

`include "netRouter.v"
module netRouter_tb;
reg  P, Q, R, S;    
wire Output; 
Network_Router test(P, Q, R, S, Output); 
initial 
begin 
//Dump results of the simulation to netRouter.vcd
$dumpfile("netRouter.vcd");
$dumpvars;
P <= 0; Q <= 0; R <= 0; S <= 0;
#5 
P <= 0; Q <= 0; R <= 0; S <= 1; 
#5 
P <= 0; Q <= 0; R <= 1; S <= 0;
#5 
P <= 0; Q <= 0; R <= 1; S <= 1;
#5
P <= 0; Q <= 1; R <= 0; S <= 0;
#5
P <= 0; Q <= 1; R <= 0; S <= 1;
#5
P <= 0; Q <= 1; R <= 1; S <= 0;
#5
P <= 0; Q <= 1; R <= 1; S <= 1;
#5
P <= 1; Q <= 0; R <= 0; S <= 0;
#5
P <= 1; Q <= 0; R <= 0; S <= 1;
#5
P <= 1; Q <= 0; R <= 1; S <= 0;
#5
P <= 1; Q <= 0; R <= 1; S <= 1;
#5
P <= 1; Q <= 1; R <= 0; S <= 0;
#5
P <= 1; Q <= 1; R <= 0; S <= 1;
#5
P <= 1; Q <= 1; R <= 1; S <= 0;
#5
P <= 1; Q <= 1; R <= 1; S <= 1;
end 
initial 
begin 
$monitor("time=%4d: %b %b %b %b : Output = %b",$time,P, Q, R, S, Output);   
end 
endmodule

Upvotes: 0

Views: 1485

Answers (1)

Oldfart
Oldfart

Reputation: 6269

You have an initial in the Network_Router module.
Replace it with an always @ ( * )

That initial is executed once when the code start and then never again. When the code starts all your reg values are x.

Upvotes: 1

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