What does '1 mean in verilog?

Question

I have a register with 4bits.

 reg[3:0] a;

And I want to assign a single bit to it like

 a <= '1;

Apparently it is not the same 1'b1 and 1. I am new to verilog and not sure about its syntax. Can anyone enlighten me please.

Answer 1

Just to answer the original question,
To assign '1' to a[3:0], do one of the following (assuming you're in an always block):

a <= 4'b1;    // binary 1 in 4 digits
a <= 4'h1;    // hexadecimal 1 in 4 digits
a <= 4'd1;    // decimal
a <= 4'b0001; // I prefer this syntax with explicit zero padding

Each of the above assignments can also explicitly specify the range of the signal:

a[3:0] <= 4'h1;

Note that the assignment <= could be replaced with = depending on your needs.

Answer 2

This sets all bits to 1, I believe.