CODEWITHSUNDEEP
syntaxverilog
Arpine Aleksanyan
Arpine Aleksanyan

Reputation: 23

Verilog syntax explanation

I'm viewing a verilog code and I've met a strange syntax "<+" which I could not find any kind of explanation to it, i hope there are some users that can tell me what does it to

so here is the line

V(out) <+ transition(aout, td, tt);

if you need more information of the verilog code.

Thank you

Upvotes: 2

Views: 182

Answers (1)

Morgan
Morgan

Reputation: 20544

It is not part of Verilog but Verilog-AMS, it might also be part of Verilog-A.

The spec is available from Accellera.

Example usage from section 1.3.4.1 of Verilog-AMS 2.4 2014:

module shiftPlus5(in, out);
  input in;
  output out;
  voltage in, out; 
  analog begin
    V(out) <+ 5.0 + V(in);
  end
endmodule

My understanding is that the <+ is used to describe voltage and current flows between nodes in your AMS models.

Upvotes: 4

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