CODEWITHSUNDEEP
verilog
Jiaqi Lee
Jiaqi Lee

Reputation: 11

Basic questions about Verilog

Why adding the concatenation operator can rand a postive value from 0~59?

reg [23:0] rand;
rand = {$random} % 60;

Why the concatenation operator {} can make such difference?

Upvotes: 0

Views: 72

Answers (1)

Serge
Serge

Reputation: 12384

from IEEE-1364

17.9.1 $random function. The system function $random provides a mechanism for generating random numbers. The function returns a new 32-bit random number each time it is called. The random number is a signed integer; it can be positive or negative.

Result of concatenation {} is always an unsigned number. This is not spelled explicitly in the standard, but even the example (from the standard) which you cited implies it.

There is no difference between signed and unsigned numbers in their bit representations. Only certain operation care about the signs of the operands, including %.

A 32-bit signed integer can represent values between -2,147,483,648 and 2,147,483,647, therefore the results of $random % 60 will be between -59 and 59.

A 32 bit unsigned integer can represent values between 0 and 4,294,967,295, therefore the result of {$random} % 60 will be from 0 to 59.

Upvotes: 2

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