CODEWITHSUNDEEP
verilog
dana
dana

Reputation: 15

Logic behind Verilog code

input x;
input y;
input[10:0] z;

wire a;

assign a = x & y & (|z);

I'm looking at a code and don't understand what the line on assign does. An explanation as to what this line means would be appreciated!

Upvotes: 1

Views: 238

Answers (2)

Krouitch
Krouitch

Reputation: 626

z is a eleven bit wide signal.
| is the or reduction of a signal.
(|z) will be true(1) if there is at least one bit in z that is 1. On the other hand, (|z) will be false(0) if all bits in z are 0. This means that the or reduction of a signal is the short way to test if a signal is 0.

|z <==> z==0;

& is the bitwise and. It means that for a multibit signal, it will perform the and operation between each bit index. The result will the be the same size as the inputs. e.g: 

wire [2:0] signal1, signal2, result;
assign result = signal1 & signal2;

is equivalent to(bit to bit):

assign result[0] = signal1[0] && signal2[0];
assign result[1] = signal1[1] && signal2[1];
assign result[2] = signal1[2] && signal2[2];

or(with concatenation):

assign result = {signal1[0] && signal2[0],signal1[1] && signal2[1],signal1[2] && signal2[2]}

In your expression though, as all the signals are 1 bit wide (a,b and (|z)) so & or && can be used equivalently.

A schematic doing what you expression states with simple 2-inputs gates is the following:

Simple gates schematic of the assignment

More informations on operators and how translating them in hardware can be found on this site.

Upvotes: 1

Matthew
Matthew

Reputation: 13937

The wire a is driven by some combinational logic. In that combinational logic all the bits of input [10:0] z are ORed together (that's what |z means). Then the result of that ORing (ie the output of an 11-input OR gate) is ANDed together with inputs x and y. The result of that ANDing (ie the output of that 3-input AND gate) is assigned to wire a (ie that 3-input AND gate drives wire a).

Upvotes: 0

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