CODEWITHSUNDEEP
if-statementverilog
mnat2310
mnat2310

Reputation: 19

Verilog: Why is there a if(0) if if(1) is always true?

I have the verilog always block as below: 

always @ (a)
begin

  if(1) begin
    ..
  end 

  if(0) begin
    ...
  end

end

Does if(1) mean that this statement is executed all the time once the always block is triggered?
Then what is the point having if(0)? When is it executed?

Note: This is a legacy code, I'm not the owner of it.

Upvotes: 1

Views: 1750

Answers (2)

user1084944
user1084944

Reputation:

I don't know if it's the intent here, but that sort of construct allows you to write source code that contains several different blocks of code, and to quickly change which one(s) you want in the source by changing which conditional has the 1.

For example, they might contain two different ways of implementing the same thing, and this makes it easier to switch back and forth if you need to test which one gives better performance.

Or, it might be about how many options you want to include in the source.

Or, sometimes, it's a form of version control and lets you keep old code around until you're sure you don't need it anymore.

Upvotes: 6

GolezTrol
GolezTrol

Reputation: 116110

Someone probably added this to disable a whole block of code. Basically as if it is inside a block comment. This is particularly useful if a piece of code already contains block comments. But it's a bit hacky too, and I wouldn't use it in production code, and certainly not without adding a comment.

Upvotes: 3

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