CODEWITHSUNDEEP
verilogconditional-operator
Ellen Spertus
Ellen Spertus

Reputation: 6805

Is there ever a reason for "? 1 : 0" in Verilog?

Computer Organization and Design (5th edition) by Hennessy and Patterson includes this Verilog code in Figure B.5.15 (p. B-37):

ALUOut <= A < B ? 1:0;

Is there any reason not to write this simpler statement instead:

ALUOut <= A < B;

In general, is there ever a reason to write "? 1 : 0" in Verilog?

Upvotes: 3

Views: 535

Answers (1)

dave_59
dave_59

Reputation: 42698

The only people that can answer why they chose one way or the other are the authors. Many of the same people prefer to write if (expr != 0) instead if (expr). Maybe they come from VHDL and want to be more explicit.

The only reason I can think of why writing expression ? 1: 0 might be needed is when the expression evaluates to 'z and you want to convert it to 'x.

Upvotes: 3

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