CODEWITHSUNDEEP
recursionverilogsystem-verilog
Vineeth Ananthula
Vineeth Ananthula

Reputation: 95

How does recursion work in Verilog?

I was supposed to apply recursion in Verilog . The code which I have designed doesn't show any error. Please have a look at my code where the task (splitt00) is recursively called. Does Verilog support recursion and how can I implement a recursive logic?

task split00;
input [0:n-1] a;
input   [0:n-1] b;
input [0:n-1] num0;
output [0:2*n-1] s;
reg [0:n-1] a0,b0,u0,v0,w0,s0,s1,a1,b1,a2,b2,u1,w1,v1;
reg [0:n-1] num00;
begin
     num00=num0;
     if(num00==2)
        begin
            u0=(a/10)*(b/10);
            w0=(a%10)*(b%10);
            if (((a%10-a/10)*(b%10-b/10))<0)
            begin
            v0=((a%10-a/10)*(b%10-b/10))*-1;
            s=u0*100+(u0+w0+v0)*10+w0;
            end
            else
            begin
            v0=((a%10-a/10)*(b%10-b/10));
            s=u0*100+(u0+w0-v0)*10+w0;
            end

        end

    else
    begin
    a0=a/(10**(num00/2));
    b0=a%(10**(num00/2));
    a1=b/(10**(num00/2));
    b1=b%(10**(num00/2));
    split00(a0,a1,num00/2,u1);
    split00(b0,b1,num00/2,w1);
    if((a1-a0)<0 && (b1-b0)>0)
        begin 
        a2=a0-a1;
        b2=b1-b0;
        split00(a2,b2,num00/2,v1);  
        s=u1*(10**num0)+(u1+v1+w1)*(10**(num0/2))+w1;
        end
    else if((a1-a0)>0 && (b1-b0)<0)
        begin
        a2=a1-a0;
        b2=b0-b1;
        split00(a2,b2,num00/2,v1);  
        s=u1*(10**num0)+(u1+v1+w1)*(10**(num0/2))+w1;
        end
    else if((a1-a0)<0 && (b1-b0)<0)
        begin
        a2=a0-a1;
        b2=b0-b1;
        split00(a2,b2,num00/2,v1);  
        s=u1*(10**num0)+(u1-v1+w1)*(10**(num0/2))+w1;
        end
    else 
        begin
        a2=a1-a0;
        b2=b1-b0;
        split00(a2,b2,num00/2,v1);  
        s=u1*(10**num0)+(u1-v1+w1)*(10**(num0/2))+w1;
        end
    end
end 
endtask

Upvotes: 3

Views: 3916

Answers (1)

dave_59
dave_59

Reputation: 42698

What you have coded here is Verilog-1995, which does not support recursion. The arguments to your task, and all the local variables inside it are static variables, which means there is only one copy of them for all entries into the task. Verilog-2001 added automatic tasks and functions, which changes the lifetime so that each entry creates a new copy of those variables. The way you would code that is by adding the automatic keyword.

task automatic split00(
  input [0:n-1] a,
  input   [0:n-1] b,
  input [0:n-1] num0,
  output [0:2*n-1] s);

In SystemVerilog, I would use a function instead of a task for any routine that is combinational logic, and change the keyword reg to logic

function automatic void split00(
    input [0:n-1] a,
    input   [0:n-1] b,
    input [0:n-1] num0,
    output [0:2*n-1] s);
logic [0:n-1] a0,b0,u0,v0,w0,s0,s1,a1,b1,a2,b2,u1,w1,v1;
logic [0:n-1] num00;

In order to synthesize a recursive function, you have the same coding restrictions as any loop. The synthesis tool needs to unroll the recursion into a fixed number of entries of the function. It does this by in-lining the function in to the body of code that made the call to the function.

Upvotes: 5

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