Simple Questions to Verilog I can't seem to find answers to:

Question

1. In a Verilog module, what is the proper terminology for arguments?

2. What does a variable default to when it's not defined?

Answer 1

They are called ports . A Verilog module cannot be called like a function, as it is meant to represent a hardware module with input , output , bi-directional pins etc , so it can only be instanced. These instances can be connected to each other again via their ports. These ports bring in and take out data/value/signals into and out of the modules. Hence ports have direction associated with them. Unlike an arguments in a function which only passes on the value when the function is called , once a connection is made to a port ( via a wire/reg (register) / ...) any change to the connected variable is transferred to the module via the port automatically.

link to a module- port explanation.

http://www.asic-world.com/verilog/syntax2.html

Verilog does have functions and tasks which take arguments.

http://www.asic-world.com/verilog/task_func1.html

Uninitialized variables take on unknown value represented by "x" .

There are a few nuances to it

unconnected wire , tri will be tri-state represented by "z"

any 4 state logic - reg , integer , time will default to "x" real type to 0 .

Answer 2

A module in Verilog represents hierarchy that is only used for grouping objects by name and replicating those objects. When you run a simulation or synthesize to hardware, that hierarchy gets flattened. Ports of a module join two signal names together, and after flattening, there is only one signal with multiple names. So modules are structurally connected through ports.

The term argument is terminology from software that usually represents a object that gets copied or referenced when you procedurally call a routine like a function or task.

For your second question, if you refer to a variable without defining it, that is usually a compiler error. There is one exception to that for lazy engineers. If you refer to a undefined variable in a port connection, that variable is implicitly declared as a 1-bit wire. If nothing drives that wire, it has the default value 'z which is treated the same as 'x in any expression.

This feature was originally intended for automatically generated gate-level net-lists where every signal is a 1-bit wire, but causes many problems for RTL descriptions. We strongly recommend that use use the compiler directive `default_nettype none to prevent careless typos.