CODEWITHSUNDEEP
syntaxverilog
klenium
klenium

Reputation: 2617

Where are input/output needed?

I saw this code in an older exam example:

module cnt512 (
input clk, R, E, output reg [8:0] q
);

Is this a valid syntax? I know these are valid:

module cnt512 (clk, R, E, q);
input clk;
input R;
input E;
output reg [8:0] q;

module cnt512 (
    input clk,
    input R,
    input E,
    output reg [8:0] q
);

But I can't see anywhere that shorter variant. Since I saw it in an university's exam, I wouldn't think they made a such mistake.

Upvotes: 1

Views: 46

Answers (1)

Greg
Greg

Reputation: 19112

I'm assuming you forgot the semicolon in the first two, but otherwise it is legal. Most people would put different port directions on different lines, like below, but that is just for readability. You can put it all on one line if you are trying to reduce space.

module cnt512 (
  input clk, R, E,
  output reg [8:0] q
);

The port direction and data type of the previous port is carried over to the next port if not defined.

Refer to IEEE Std 1800-2012 § 23.2.2 Port declarations for full explanation. Specific example in § 23.2.2.2 ANSI style list of port declarations. IEEE1800 is SystemVerilog, the successor of Verilog. Port declaration are the same unless you go back to Verilog 1995.

Upvotes: 1

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