CODEWITHSUNDEEP
syntaxverilog
Tomer Polski
Tomer Polski

Reputation: 41

why do i get syntax eror?

i want to make the leds on my zed board to blink from one side to the other and this is my code : 

module blinky(
    input wire clk,
    input wire reset,
    input wire direction,
    output reg [7:0] leds
    );

always @(posedge clk) begin 


                    if (reset==1) begin
                    // reset the leds to the default state
                        leds <=1;

                    end
                    else begin 
                          // move the light from right to left 
                          if (direction == 1)
                          // standard way to do a rotation in Verilog 
                              leds<= {leds[6:0],leds[7]};
                          end 

            // move the light from left to right 
            else begin 
            leds <= {leds[0],leds[6:1]};
           end
         end

    end


endmodule

how ever when i write this statment :

else begin leds <= {leds[0],leds[6:1]}; end

i get syntax eror . I cant understand why . could anyone help me get the syntax right ? i searched google and found couple of methods but all give me the same eror.

Upvotes: 0

Views: 74

Answers (1)

Oldfart
Oldfart

Reputation: 6269

I think you forgot a begin after if (direction == 1):

One of the reason it is difficult to spot is that you indenting is rather erratic.

Coding outline is very personal. I prefer my begin in line with my end as my editor gives a nice matching line. I also use 3 spaces as indent because with deep indenting I can't keep track of where everything is. But as I said that is personal:

enter image description here

Upvotes: 2

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