CODEWITHSUNDEEP
verilog
Harjiven Dodd
Harjiven Dodd

Reputation: 1

Verilog Syntax Error, I can't find the cause?

I am just starting out in Verilog, and can't seem to find the error in the code below, thank you in advance!

    module sortTwo(input logic signed [15:0] A[1:0],
            output logic signed [15:0] B[1:0]);
      always @* begin
          if (A[0]>A[1])
            begin
            assign B[1] = A[0];
            assign B[0] = A[1];
            end
        else 
            begin
            assign B[1] =A [1];
            assign B[0] = A[0];
            end
        end
    endmodule //end sortTwo

Upvotes: 0

Views: 2974

Answers (2)

dave_59
dave_59

Reputation: 42673

IcarusVerilog does not support most of SystemVerilog, and may require a switch to enable what it does support. logic is a SystemVerilog keyword. Try adding -g2012

Upvotes: 2

Eugenio Lyatte
Eugenio Lyatte

Reputation: 19

You can't use assign in always blocks. To fix your problem you need replace assign B[1] = A[0]; to B[1] = A[0];

Upvotes: 1

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