CODEWITHSUNDEEP
inputcompiler-errorsverilog
a_mozart
a_mozart

Reputation: 13

Verilog input error

I have a couple of errors in my verilog code that pop up when I compile. I believe they are all related. But I can't figure out what the error is. Any help will be greatly appreciated.

The errors are: Two for the input

vlog_a: Error 31004 Syntax error near `input' found

blog_a: Error 31004 Syntax error near 'output' found

module threeBitComparator; 
  input A2,A1,A0;
  input B2,B1,B0;
  output E,GE; //E-Equal,  GE-Greater than or Equal to

  wire X1,X2,X3; //xnor gate
  wire Y1,Y2,Y3,Y4,Y5,Y6; // and & or gates

  xnor
      G1a(X1,A2,B2),
      G1b(X2,A1,B1),
      G1c(X3,A0,B0);

  and
     G2a(Y1,A2,~B2),
     G2b(Y2,A1,~B1),
     G2c(Y3,A0,~B0),
     G2d(Y4,X1,Y2),
     G2e(Y5,X1,X2,Y3),
     G2f(E,X1,X2,X3);

  or
    G3a(Y6,Y1,Y4,Y5),
    G3b(GE,Y6,E);
endmodule

Upvotes: 1

Views: 473

Answers (2)

Greg
Greg

Reputation: 19104

You declared your inputs and outputs but you haven't declared a port list. Your module header needs to look like below code to be IEEE 1364-1995 complaint

module threeBitComparator(A2,A1,A0,B2,B1,B0,E,GE); // <-- port list
  input A2,A1,A0;
  input B2,B1,B0;
  output E,GE; //E-Equal,  GE-Greater than or Equal to

Or you can use the ANSI style header introduce in IEEE Std 1364-2001. This style works on any modern Verilog simulator.

module threeBitComparator(
  input A2,A1,A0,
  input B2,B1,B0,
  output E,GE ); //E-Equal,  GE-Greater than or Equal to

Upvotes: 1

Rahul Behl
Rahul Behl

Reputation: 381

I think you forgot to declare your input and output in the module port lists. Adding A2, A1..., etc to the port list will solve the compilation errors.

You can check the updated code here.

Upvotes: 0

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