CODEWITHSUNDEEP
verilog
Haider Iftikhar
Haider Iftikhar

Reputation: 11

In verilog I have an error that I can't get past

module data_path(
  input clk,
  input rst,
  input inc_pc,
  input load_mar,
  input load_mbr,
  input load_ir,
  input r_w,
  input [7:0] data_in,
  input load_ac,
  input mux_sel,
  output [7:0] ir_out);


  reg [3:0]var;
  reg [2:0]opcode;
  wire [3:0] w1,w2,w6;
  wire [7:0] w3,w4,w5;

  pc pc1(.rst(rst),.clk(clk),.inc_pc(inc_pc),.pc_out(w1));

  register1 mar(.rst(rst),.clk(clk),.load(load_mar),.in(w1),.out(w2));

  memory memory1(.add_in(w2),.data_in(data_in),.data_out(w3),.r_w(r_w));

  register2 mbr(.rst(rst),.clk(clk),.load(load_mbr),.in(w3),.out(w4));

  register1 ir(.rst(rst),.clk(clk),.load(load_ir),.in(w4),.out(w5));

  assign opcode=w4[7:5];

  if(opcode==3'b000)
    register1 ac(.rst(rst),.clk(clk),.load(load_ac),.in(w4[4:0]),.out(w6));
  else
    if(opcode==3'b001)
    begin
        assign var=w6+w4[4:0];
        register1 ac(.rst(rst),.clk(clk),.load(load_ac),.in(var),.out(w6));
    end
endmodule

Getting error: 

data_path.v line 52 expecting 'endmodule', found 'if'

Upvotes: 0

Views: 95

Answers (3)

JerryJamesO
JerryJamesO

Reputation: 11

Both prior answers correctly capture some information. You're trying to mux an input to register1 based on the opcode. A little weirdness in that you're sending in either 4b or 5b based on the if-else. I'll let it slide and assume 5b without sign extension for now. Also your output is 4b.

One other thing. Overflow in the opcode 3'b001 add (which doesn't add up in your assign) - how would one add 4b(w6) + 5b(w4[4:0]) into 4b (var) reliably?

Here's the (untested, caution) code revision (snippet of your code above).

Declare a wire that you mux per the opcode.

wire [7:0] tmpin;

Now correctly write the always to capture the behavior

always @(*) begin
   if(opcode==3'b000)        tmpin = {3'b0,w4[4:0]};
   elsif (opcode == 3'b001)  tmpin = {4'b0,w6} + w4;
end

Then you just follow with the muxed variable into a concurrent statement - the register declaration. 

register1 ac(.rst(rst),.clk(clk),.load(load_ac),.in(tmpin[4:0]),.out(w6));

Have fun!

Upvotes: 1

Kiloman
Kiloman

Reputation: 47

If 'register1' is another Verilog module, this logic will not work. In your code, you are using the output of a Verilog module (something that is not known at static-run time but that instead my change every clock cycle) to determine which of two instances to instantiate.

Instances will exist from the start of run time, and cannot be brought in and out of existence every clock cycle. Instead, you will have to create both instances of 'register1 ac' as two separate instances (with different names, and with their outputs named differently). And then use a mux (multiplexor) to select between the two output busses depending on the value of 'opcode'.

Upvotes: 1

osgx
osgx

Reputation: 94465

if usually used in the always or initial block (Procedural Blocks; so you can't check opcode with if outside of procedural block. Try to move if inside always @ (posedge clk).

You also should move register1 ac(.rst(rst),.clk(clk),.load(load_ac),.in(w4[4:0]),.out(w6)); instantiation outside of if, because you describe hardware and there is no Conditional instantiation of verilog modules

Upvotes: 1

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