CODEWITHSUNDEEP
system-verilog
Prince
Prince

Reputation: 13

How to cope with the error of the following piece of system verilog code?

schematic schematic

I would like to write system verilog code to implement this schematic (using 3 2:4 decoder and 64 3-input and gate to achieve a 6:64 decoder), and the following is my piece of code:

module Ex4( input logic [5:0] D,
            output logic [63:0] y
         );

    genvar i;
    genvar j;
    genvar k;
    integer n = 0;
    logic [3:0] y1, y2, y3;

    dec2 d1(D[1:0], y1);
    dec2 d2(D[3:2], y2);
    dec2 d3(D[5:4], y3);

    generate
      begin 
        for(i = 0; i < 3; i = i + 1) begin:flp1
            for (j = 0; j < 3; j = j + 1) begin:flp2
                for(k = 0; k < 3; k = k + 1) begin:flp3
                   and3_new a_n(y1[i], y2[j], y3[k], y[n]);
                   n=n+1; // error message comes from this line
                end
            end
        end
     end
   endgenerate  
endmodule

Note: "dec2" and "and3_new" are two modules written in advance with no problems

However, I got the following error during compilation, can anybody give me some hint? Thank you.

Error (10170): Verilog HDL syntax error at Ex4.sv(22) near text: "=";
expecting ".", or "(". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge- base/search.html and search for this specific error message number.

Upvotes: 1

Views: 389

Answers (1)

dave_59
dave_59

Reputation: 42788

You can't put a procedural assignment statement in that position. Instead of [n], use [i*16+j*4+k]. You can also do

module Ex4( input logic [5:0] D,
            output logic [63:0] y
         );
    logic [3:0] y1, y2, y3;

    dec2 d1(D[1:0], y1);
    dec2 d2(D[3:2], y2);
    dec2 d3(D[5:4], y3);

        for(genvar i = 0; i < 4; i++) begin:flp1
            for (genvar j = 0; j < 4; j++) begin:flp2
                for(genvar k = 0; k < 4; k = k + 1) begin:flp3
                   parameter n = i*16+j*4+k;
                   and3_new a_n(y1[i], y2[j], y3[k], y[n]);
                end :flp3
            end : flp2
        end : flp1

endmodule

Upvotes: 1

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