CODEWITHSUNDEEP
verilog
JoeEhab12
JoeEhab12

Reputation: 65

verilog compiler syntax error unexpected end

I am writing a test bench for AND module but it gives me the following error near "end": syntax error, unexpected end.

here is my code:

module TestAND();

reg A;
reg B;
wire C;

AND inst(A,B,C);


initial begin
 A=1;
 B=0;
 #100
end

Upvotes: 2

Views: 6799

Answers (2)

maxslug
maxslug

Reputation: 121

I see a couple things here, you have an incorrect data type: reg is only used in an always block, and so here everything should be type wire. Also if I recall correctly the primitives usually have the output first, so you would probably want AND my_and (c,a,b);

However, usually you don't use primitives directly unless you're creating libraries, and would want to use assign c = a & b; instead.

Upvotes: 0

Kamil Rymarz
Kamil Rymarz

Reputation: 408

You need to add ;after #100 and you also missing endmodule at the end.

Upvotes: 4

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