CODEWITHSUNDEEP
verilog
user122831
user122831

Reputation: 31

Unexpected "end" and "endmodule" in Test Bench?

I'm working on a Verilog project where I need to find the 9's complement of a 4-bit binary number. I wrote a module that I believe should work, but I'm having a strange error with the testbench:

module test_nine();

reg [3:0] A; //inputs

wire w,x,y,z; //outputs

integer loop_counter; //for loop counter

NinesComplement nc0(A[0],A[1],A[2],A[3],w,x,y,z);

initial
  begin

  for(loop_counter=0; loop_counter<16; loop_counter=loop_counter+1)
  begin
  #8 A=loop_counter;
  end

  #8 $finish()
  end
endmodule

When I run it, I get an error:

Unexpected token "end" and "endmodule" found.

Aren't those necessary? Just in case the error is in my main module, I'll add it below:

module NinesComplement(a,b,c,d,w,x,y,z);

//inputs
input a,b,c,d;

//outputs
output w,x,y,z;

//wires
wire ab,an,bn,cn,dn;


not #8
//creates a'
n0a(an,a),

//creates b'
n0b(bn,b),

//creates c'
n0c(cn,c),

//creates d'
n0d(dn,d);


and #8
a0a(ab,an,bn),

a0b(w,ab,cn),

a0c(y,c,c);

xor #8

x0a(x,b,c);


nand #8

n1a(z,dn,dn);

endmodule

Upvotes: 2

Views: 1683

Answers (1)

toolic
toolic

Reputation: 62037

Each statement needs to end with a semicolon. Add one after the $finish:

  #8 $finish();

Upvotes: 1

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