CODEWITHSUNDEEP
verilog
chasep255
chasep255

Reputation: 12185

Why isn't my test bench working?

I decided to start playing around with Verilog this weekend. I am really new to this and don't entirely understand what I am doing. I copied this adder code out of a PDF tutorial. The issue is that the tutorial does not give any test code to run it with. I tried to write my own but the output I am getting is zzzz. I am thinking that maybe it is trying to produce the output before the addition function has finished executing.

module addbit(a, b, ci, sum, co);
    input a, b, ci;
    output sum, co;
    wire a, b, ci, sum, co;
    assign {co, sum} = a + b + ci;
endmodule

module adder(result, carry, r1, r2, ci);
    input [3:0] r1;
    input [3:0] r2;
    input ci;
    output [3:0] result;
    output carry;
    wire [3:0] r1;
    wire [3:0] r2;
    wire ci;
    wire [3:0] result;
    wire carry;
    wire c1, c2, c3;
    addbit u0(r1[0], r2[0], ci, result[0], c1);
    addbit u1(r1[1], r2[1], c1, result[0], c2);
    addbit u2(r1[2], r2[2], c2, result[0], c3);
    addbit u3(r1[3], r2[3], c3, result[0], carry);
endmodule

module test();
    wire [3:0] a = 4'b1000;
    wire [3:0] b = 4'b0100;
    wire [3:0] result;
    wire carry = 0;
    wire ocarry;
    adder x(result, ocarry, a, b, carry);
    initial begin
        $display("%b", result);
    end
endmodule

Upvotes: 0

Views: 1386

Answers (1)

e19293001
e19293001

Reputation: 2911

the output I am getting is zzzz

The reason why you are getting an output zzzz is from your adder circuit (see mcleod_ideafix's comment below).

You might want to change you're input type of a and b as reg type so you can assign them inside a procedural block and assign them with different values.

module test();
    reg [3:0] a = 4'b1000;
    reg [3:0] b = 4'b0100;
    wire [3:0] result;
    wire carry = 0;
    wire ocarry;
    adder x(result, ocarry, a, b, carry);
    initial begin
      $display("@ %0dns a: %0d b: %0d result: %0d", $time, a, b, result);
      #1ns;
      a = 5;
      b = 6;
      $display("@ %0dns a: %0d b: %0d result: %0d", $time, a, b, result);
    end
endmodule

Using the RTL that you posted and the test bench I modified above, it will produce an output:

@ 0ns a: 8 b: 4 result: X
@ 1ns a: 5 b: 6 result: X

You're adder does not work as expected for an adder circuit.

To help you further, I created an adder circuit for you.

module adder(result, carry, r1, r2, ci);
   input [3:0] r1;
   input [3:0] r2;
   input       ci;
   output [3:0] result;
   output       carry;

   assign {carry, result} = r1 + r2 + ci;
endmodule

And a working test bench that initializes the input to 0 then loops 10 times. Inside the loop, we create a delay of 1ns and changes the input to a random value from 0 to 15. 

module test();
   reg [3:0] a;
   reg [3:0] b;
   wire [3:0] result;
   wire       carry = 0;
   wire       ocarry;

   adder x(result, ocarry, a, b, carry);

   initial begin
      $monitor("@%0dns [a: %0d] + [b: %0d] = [result: %0d] [carry = %0d] [ocarry = %0d] ", $time, a, b, result, carry, ocarry);
   end

   initial begin
      a = 0;
      b = 0;
      repeat (10) begin
         #1ns;
         a = $random % 'h10;
         b = $random % 'h10;
      end
   end
endmodule

You can run this code in edaplayground and see the output.

For every change of a, b, result, carry, ocarry, this code is executed. 

$monitor("@%0dns [a: %0d] + [b: %0d] = [result: %0d] [carry = %0d] [ocarry = %0d] ", $time, a, b, result, carry, ocarry);

Upvotes: 1

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