CODEWITHSUNDEEP
verilogsystem-verilog
Strawberry
Strawberry

Reputation: 67888

What is this syntax for in Verilog?

module exmaple(input a, b, input in[2:0], output d, e, output out[5:0])

I am new to Verilog and trying to understand what input in[2:0] means?

Upvotes: 1

Views: 441

Answers (1)

user597225
user597225

Reputation:

That isn't valid Verilog(IEEE-1364), it is SystemVerilog(IEEE-1800). SV allows ports to be declared as multi-dimensional arrays so in this case in is declared as an array of single bit wires.

Generally if you wanted a vector for a port you would use input [2:0] in which is valid in both Verilog and SystemVerilog. However if your port type cannot be a vector, such as integer or time then you would need to use this method.

Upvotes: 5

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