CODEWITHSUNDEEP
verilog
Thomson
Thomson

Reputation: 21625

What does #`DEL mean in Verilog?

I saw some statements in the form of below. What does #`DEL mean here? I cannot find its meaning easily because it contains a special character.

cmd <= #`DEL 32'b0

Upvotes: 3

Views: 1884

Answers (2)

IWantAnalogHDL
IWantAnalogHDL

Reputation: 306

The code in question delays the assignment by some amount. The #`DEL (can't use inline coding because of the backtick) has 3 parts. First, the # indicates that this is a delay statement. Next, the backtick (the character underneath the ~) indicates a preprocessor definition in Verilog; somewhere in the code you're compiling you will have something along the following lines:

`define DEL 1ns

Where 1ns might be any time value, which will be the delay. We should be clear here that there should be a backtick (under the ~) before DEL, whereas 32'b0 uses a single quote.

Upvotes: 5

Morgan
Morgan

Reputation: 20514

It is a delay statement.

Delaying the assign of value on the Righthand side to the lefthand side by the defined amount, in this case delaying cmd becoming zero.

The delay can be specified in any time or realtime format, #1 would be 1 timestep as defined by the ...

#1ns, #1us, #1ms and more are available in SystemVerilog.

A more typical case would be with a non-constant right hand side.

assign a = #1ns b;

Here a will lag b by 1 ns.

Reference to this can be found in Language Reference Manual LRM by searching for 'delay_value'.

Upvotes: 4

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