CODEWITHSUNDEEP
verilog
grander3
grander3

Reputation: 181

what is the purpose #(10) in verilog instance?

Now I'm trying to understand some verilog code as the below,

  dataproc #(10) proc01
     (

      .dout                             (dout01[9:0]),               
      .clk                              (clkin01),          
      .rst_n                            (rst_in01_n),    
      .din                              (dout[9:0])
    );

actually I didn't get the purpose of this

 #(10)

what is this? and what is the purpose in the verilog?

I'm usually using as the below way

 dataproc u_dataproc
(
...
...
)

But I never been seen the before

#(10)

update

I've update the module.

module dataproc 
  #(parameter w = 1)
   (
    input              clk,
    input              rst_n,
    input [w-1:0]      din,
    output wire [w-1:0] dout
    ); 
   
   reg [w-1:0]  NP_dout;
   assign dout = NP_dout;

endmodule

Upvotes: 0

Views: 889

Answers (1)

Karan Shah
Karan Shah

Reputation: 1992

It's a parameter, which you are overriding while making the instance of the module.

Suppose you have a module like below.

module temp();
  parameter a = 2;
  bit [a-1:0] b1;
endmodule

Now if you take instance of the above module and want to change the default parameter value (which in turn change the underlying hardware of that module), then you can do something like follow.

module abc();
  temp t1();
  temp #(4) t2(); // Changes the default parameter value

  initial
  begin
    $display("Size of t1.b1 - %0d", $size(t1.b1));
    $display("Size of t2.b1 - %0d", $size(t2.b1));
  end
endmodule

// Output 
Size of t1.b1 - 2
Size of t2.b1 - 4

Please note that parameters must be having a value before runtime or in elaboration time. So you can't change parameters during simulation run.

Upvotes: 1

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