CODEWITHSUNDEEP
verilogsystem-veriloghardwaredigital
Paulo
Paulo

Reputation: 135

Why does carry disappear in addition?

I have the following code:

logic [3:0] a = 4'1010;
logic [3:0] b = 4'b0111;
logic [3:0] f = 4'b1000; // ~b
logic [4:0] c;
logic [4:0] d;
logic [4:0] e;
 
    assign c = a + b;     // this gives a carry in c
    assign e = a + f;     // this gives a carry in f
    assign d = a + ~b;    // this should give a carry but the carry disappears

Why is it that when I add a + ~b, the carry disappears? What does the ~ operator do to the expression that the width becomes 4 instead of 5, or whatever is happening?

I tried simulations.

Upvotes: 1

Views: 56

Answers (1)

toolic
toolic

Reputation: 62236

Refer to IEEE Std 1800-2023 section 11.6 Expression bit lengths.

The behavior is due to the fact that the ~b is evaluated in a context-determined manner. In this statement:

assign d = a + ~b;

The left-hand side (d) is 5 bits wide, and all signals on the right-hand side (RHS) are 4 bits wide. This means that the expression on the RHS is evaluated as 5 bits, not 4 bits.

In this context, when b is 4'b0111, it is extended to 5 bits to become 5'b0_0111. Then all 5 bits are inverted to become 5'b1_1000 (decimal 24). Since a is decimal 10, a + ~b becomes 10 + 24 = 34, which is 6'b10_0010. Since only 5 bits can be retained, that value is truncated to 5'b0_0010.

What does the ~ operator do to the expression that the width becomes 4 instead of 5, ... ?

The ~ does not force the width of the expression to be 4, as explained above.

Upvotes: 1

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