Sean Sandler
Reputation: 1
How to create a verilog testbench
I need to create a verilog testbench in eda playground to test the following code
module SmartTrafficLight (
input wire R1, R2, R3,
output wire G1, G2, G3
);
assign G1 = R1;
assign G2 = R2 & ~R1;
assign G3 = R3 & ~R2 & ~R1;
endmodule
How would I go about doing this
Upvotes: -1
Views: 34
Answers (0)
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