CODEWITHSUNDEEP
verilogtest-bench
John_cena
John_cena

Reputation: 23

Getting an error calling a task in verilog testbench

I've following tasks with different input vectors (that part is not written for simplicity) in my Verilog testbench

task input_set_1;
    begin
    end
endtask

task input_set_2;
    begin
    end
endtask

task input_set_3;
    begin
    end
endtask

task input_set_4;
    begin
    end
endtask

I'm trying to call only one of them during the testbench simulation using the below task

task input_calling;
    integer i;
    begin
        i = $urandom_range(1, 4);
        input_set_i;
    end
endtask

initial begin
    #3;
    input_calling;
end

I'm expecting with each test run, any of the input_set_1, or input_set_2 or input_set_3 or input_set_4 will be called based on the random number i=1 to 4, however, I'm getting an error saying input_set_i is not defined. I suspect some string to int mismatch is preventing I to take randomized value in the input _set_i task.

Upvotes: 1

Views: 633

Answers (1)

Serge
Serge

Reputation: 12344

You are trying to do something which is impossible in verilog (as well as in any non-scripting language). Name of the task is a compile-time element which must be known to the compiler at compilation time. i is a run-time, dynamic element. You cannot use run-time objects to modify compile-time objects.

So, your best bet is to use dynamic language features to make your program work, e.g. if statements. Here is an example:

module top;
  task a;
    $display("a");
  endtask
  task b;
    $display("b");
  endtask

  initial begin
    for (int k = 0; k < 4; k++) begin
      automatic int i = $urandom_range(2,1);
      if (i == 1)
        a;
      else if (i == 2)
        b;
    end
  end
endmodule

Upvotes: 3

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