CODEWITHSUNDEEP
taskverilogsystem-verilogtest-bench
J. Damone
J. Damone

Reputation: 23

Task does not update testbench sclk

I'm trying to understand why my signal is not updating when it is processed by the task.

As you could see below, the problem is related to the signal that internally on the task are changing correctly but even in a hierarchical call do not change the signal outside the task.

//-------------------------------
timeunit 1ps;
timeprecision 1ps;

`define CLK_HALF_PERIOD             10
`define SCK_HALF_PERIOD             30

module tbench ();

logic      clk;
logic      sclk;
logic      RST;

hwpe_stream_intf_stream MOSI();
hwpe_stream_intf_stream MISO();
logic      try;
 initial begin
 spi_send (.addr({1'b1,3'b111,12'd1,16'd0  }),
           .data(1), 
           .MISO(try), 
           .MOSI(MOSI.data), 
           .SCK(sclk)); 
 end

  always
  begin
    # `CLK_HALF_PERIOD clk = 1;
    # `CLK_HALF_PERIOD clk = 0;
  end
 
task automatic spi_send (
        input  logic [31:0] addr,
        input  logic [31:0] data,
        input  logic        MISO, // not used
        ref    logic     MOSI,
        ref    logic      SCK
    );
        integer i = 0;
        $display ("add=%-32d",addr );
        for (i=0; i<32; i=i+1) begin
        //$display("add", 31-i , "          MOSI  ",MOSI);
        
           // MOSI = ;
            MOSI  = addr[31-i];
            tbench.try  = MOSI;
            #`SCK_HALF_PERIOD
            tbench.sclk   = 1'b1;
            #`SCK_HALF_PERIOD;
            tbench.sclk  = 1'b0;
            $display("add", addr[30-i] , "          MOSI  ",MOSI);
        end
 endtask

endmodule

tbench.sclk and MOSI are not changing globally, but only locally.

Here is the interface:

interface hwpe_stream_intf_stream() ;

  logic                    valid;
  logic                    ready;
  logic                     data;
  logic [8/8-1:0] strb;

  modport source (
    output valid, data, strb,
    input  ready
  );
  modport sink (
    input  valid, data, strb,
    output ready
  );

endinterface

waveform

Upvotes: 2

Views: 77

Answers (1)

toolic
toolic

Reputation: 62037

You need to zoom in to the beginning of your waveforms to see sclk toggling. It toggles between 0 and 2000ps, then stops toggling.

You can add this to your testbench to stop the simulation much sooner to make it more obvious:

initial #3ns $finish;

enter image description here

Upvotes: 1

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