CODEWITHSUNDEEP
verilogsystem-verilogtest-bench
Atinesh
Atinesh

Reputation: 1910

Explain this syntax error in testbench file

I'm trying to create a testbench file for the sequential circuit in Modelsim (Verilog). But, I'm getting the following syntax error.

** Error: (vlog-13069) /Assignment_2x2_tb.v(6): near "initial": syntax error, unexpected initial, expecting ';' or ','.

Here's my code

module seq_circuit1_tb;
reg x,clk;
wire q;
seq_circuit1 seqct(x, clk, Q0, Q1)
//Module to generate clock with period 10 time units
initial begin
  forever begin
  clk=0;
  #10
  clk=1;
  #10
  clk=0;
  end
end
initial begin
  x=0;
  #50
  x=0;
  #50
  x=1;
  #50
  x=1;
  #50
end
endmodule

Why am I getting this error?

Upvotes: 2

Views: 3614

Answers (2)

Prashant
Prashant

Reputation: 362

The initial block cannot end with a delay. You need to have some statement after the last #50 as follows

initial begin
  x=0;
  #50
  x=0;
  #50
  x=1;
  #50
  x=1;
  #50 $finish;
end
endmodule

or 

initial begin
  x=0;
  #50
  x=0;
  #50
  x=1;
  #50
  x=1;
  // last #50 removed
end
endmodule

Upvotes: 0

MikeCAT
MikeCAT

Reputation: 75062

You need a semicolon (;) after the line seq_circuit1 seqct(x, clk, Q0, Q1).

Upvotes: 2

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