CODEWITHSUNDEEP
veriloghdl
Soheil Shababi
Soheil Shababi

Reputation: 119

Error when creating a task in separate file in verilog

module tb();

    reg [7:0] a = 1;
    reg [7:0] b;

    initial begin
      AddTask(a, b);
      $display("%d", b);
    end

    task AddTask;

        input [7:0] a;
        output reg[7:0] b;

        begin
          b = a + 1;
        end

    endtask


endmodule

The above code is compiled and simulated correctly; But I want to cut the task "AddTask" from the module "tb.v" and place it in a separate module "AddModule.v"(that is in a separate file) for clear coding. When I do this, modelsim can compile it but can't simulate it and give the error: " Unresolved reference to 'AddTask' ". Although I include AddModule.v, it can't recognize AddTask. Can you help me please, what's the wrong ? 

module tb;

    reg [7:0] a = 1;
    reg [7:0] b;

    `include "AddModule.v"

    initial begin
      AddTask(a, b);
      $display("%d", b);
    end
 endmodule

AddTask in a separate file:

module AddModule;

    task AddTask;

        input [7:0] a;
        output reg[7:0] b;

        begin
          b = a + 1;
        end

    endtask

endmodule

Upvotes: 1

Views: 1808

Answers (1)

andrsmllr
andrsmllr

Reputation: 1223

The problem is probably the nested module declaration. This is not allowed in Verilog, however is possible in SystemVerilog.
Try to declare only the task AddModule() in a separate file without a surounding module declaration. This file can then be included within the scope of another module, e.g. within your testbench (as in your example code).

Upvotes: 1

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