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FritzDC
FritzDC

Reputation: 507

Real-life use of SLA operator in VHDL

Most, if not all, VHDL textbooks casually list the arithmetic operators and amongst them even more so casually the Shift Left Arithmetic (SLA) as shift left that fills with rightmost element. Although even wikipedia disagrees with this definition, I have never seen anyone to even blink an eye to this definition, it's just taken in with a face value, "yup, makes sense".

However, the apparent complete uselessness of filling with the rightmost value in binary arithmetics made me to wonder - has anyone found a really good use for SLA in real life?

(I'm not against the existence of SLA, nor want to eradicate it from VHDL. This is just a bit of fun for the Easter holidays...)

Upvotes: 5

Views: 5434

Answers (2)

JHBonarius
JHBonarius

Reputation: 11281

This site mentions:

At one point, there were actual shift operators built into VHDL. These were: srl, sll, sra, sla. However these shift operators never worked correctly and were removed from the language. This website goes into great detail about the history of these VHDL shift operators and discusses why they have been replaced by shift_right() and shift_left() functions.

However the link is broken.

The wikipedia page you link shows something very important

The VHDL arithmetic left shift operator [sla] is unusual. Instead of filling the LSB of the result with zero, it copies the original LSB into the new LSB. While this is an exact mirror image of the arithmetic right shift, it is not the conventional definition of the operator, and is not equivalent to multiplication by a power of 2. In the VHDL 2008 standard this strange behavior was left unchanged (for backward compatibility) for argument types that do not have forced numeric interpretation (e.g., BIT_VECTOR) but 'SLA' for unsigned and signed argument types behaves in the expected way (i.e., rightmost positions are filled with zeros). VHDL's shift left logical (SLL) function does implement the aforementioned 'standard' arithmetic shift.

I.e. now we have the peculiar situation that sla behaves differently for different data types. That sounds like a very stupid thing to me.

However, this is expected... in my experience IEEE standardization committees mostly consist of a lot of older men, some who where there when the committee started (<'87). The rest are representatives of companies, that also don't like change. If sla etc. would be removed, this would mean a lot of old code would have to be rewritten. Then after months of discussion they decide to keep the old folks happy by keeping the old behavior for old data types, and changing the behavior for new data types....

edit

To make it more awkward, it seems sla is not defined for the std_logic_vector and unsigned types and such... But it comes back for the ufixed type and such. So I've managed to write some (vhdl-2008) code demonstrating the difference in behavior:

entity test_e is
end entity;

library ieee;

architecture test_a of test_e is
    constant value1 : bit_vector(3 downto 0) := "0001";
    constant value2 : bit_vector(3 downto 0) := value1 sla 2;

    use ieee.fixed_pkg.all;
    constant value3 : ufixed(3 downto 0) := to_ufixed(1,3,0);
    constant value4 : ufixed(3 downto 0) := value3 sla 2;    
begin
end architecture;

When simulating, value2 will hold "0111" and value4 will hold "0100".

Upvotes: 3

Roman
Roman

Reputation: 385

Of course, when you need to multiple to 2^n, you just need to SLA to n bit.

I use it in current project, to reduce used resources of FPGA, before division I use SRA, in result I get smaller number than was, use division and then use SRL to get right scale of the value.

It looks like, C=A/B, with reducing C*N=(A/N)/B.

You get some error in C, but reduce used resources.

Upvotes: -1

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