CODEWITHSUNDEEP
vhdl
Martin
Martin

Reputation: 47

VHDL operator argument type mismatch

I have a very simple operator problem in VHDL. I try to compare some inputs with logical operators but get an error message...

entity test is
 port (
  paddr              : in  std_logic_vector(15 downto 0);
  psel                : in  std_logic;
  penable              : in  std_logic;
  pwrite              : in  std_logic
 );  
end entity test;

signal wrfifo_full       : std_logic; 

process (paddr, psel, penable, pwrite, wrfifo_full) is
begin
  if (((paddr(8 downto 2) = "1000000")) and (psel and penable) and (pwrite and not(wrfifo_full))) then
    dt_fifo_wr_i <= '1';
  else
    dt_fifo_wr_i <= '0';
  end if;

end process;

Unfortuantely, I get then the following error message:

if (((paddr(8 downto 2) = "1000000")) and (psel and penable) and (pwrite and not(wrfifo_full))) then | ncvhdl_p: *E,OPTYMM (hdl/vhdl/test.vhd,523|43): operator argument type mismatch 87[4.3.3.2] 93[4.3.2.2] [7.2]

Anyway sees the problem?

Cheers

Upvotes: 3

Views: 3024

Answers (2)

Martin Thompson
Martin Thompson

Reputation: 16792

As George said, you have to currently convert all your std logics to booleans.

In VHDL-2008 however, there is a new conditional operator (??) which is applied implicitly to statements such as yours, which means they will work as you hoped. You'll have to enable VHDL-2008 support on you compiler (or whinge at your supplier to get with the times :)

This book is a good read on all the new bits that VHDL2008 gives us:

VHDL-2008 Just the new stuff

Section 4.4 covers the conditional operator

Upvotes: 5

George
George

Reputation: 1132

psel, penable, pwrite and wrfifo_full are all std_logic.

In vhdl, to write the test they way you have, they would need to be boolean.

Instead write the code so that you are comparing their values to 1 or zero.

(paddr(8 downto 2) = "1000000"     and 
 psel   = '1' and penable     ='1' and 
 pwrite = '1' and wrfifo_full = '0')

Upvotes: 7

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