Variable length unsigned in VHDL function

Question

I want to create an unsigned in a function whose length is determined by the function parameters. I thought that was a legit thing to do- pretty sure I've even done it before, but maybe not- but ISE 14.7 doesn't think so (I know, I know. I have to use ISE because we're resurrecting an old system).

The purpose of the function is divide by a power of 2 and round the result. ISE doesn't like that I'm subtracting num_bits from the length of the input when declaring truncated. Is there a better way to do this?

 function my_round(data_in : in unsigned; num_bits : in integer) return unsigned is
     variable truncated : unsigned(data_in'left - num_bits downto 0);
  begin
     truncated := data_in(data_in'left downto num_bits);
     if my_and_reduce(truncated) = '0' and data_in(num_bits-1) = '1' then
        truncated := truncated + 1;
     end if;
     return truncated;
  end my_round;

The error message that ISE gives me when trying to synthesize the code is "Constant value expected for expression (31 - num_bits)"

Answer 1

It turned out that iSim, the Xilinx ISE simulator, did not have an issue with the function, so it appears to me that the problem is not at the language level, rather it's an ISE implementation problem.

I changed the function to the following, since I always called it with a num_bit parameter of 14, and it built fine.

 function my_round(data_in : in unsigned; dummy : in integer) return unsigned is
     constant num_bits : integer := 14;
     variable truncated : unsigned(data_in'left - num_bits downto 0);
  begin
     truncated := data_in(data_in'left downto num_bits);
     if my_and_reduce(truncated) = '0' and data_in(num_bits-1) = '1' then
        truncated := truncated + 1;
     end if;
     return truncated;
  end my_round;