CODEWITHSUNDEEP
vhdlxilinx-ise
DarkestSoul1992
DarkestSoul1992

Reputation: 9

VHDL entity definition

I am using a few resources on the internet to learn processor and motherboard design and I came across the error: VHDL: Syntax error near end. I am fairly new to this and can't seem to pin-point the fault. Any help would be greatly appreciated.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ROM is
port (
    ADDR : in std_logic_vector (31 downto 0);
    D_IN : in std_logic_vector (63 downto 0);
    D_OUT : out std_logic_vector (63 downto 0);
    CLK : in std_logic;
    WE : in std_logic;
    EN : out std_logic
)
end ROM;

architecture rom_arch of ROM is

    constant INVALID_DATA : std_logic_vector (63 downto 0) := (others => 'X');
    subtype DATA_ROM_WORD is std_logic_vector (63 downto 0);
    type DATA_ROM_TABLE is array (0 to (2**3)-1) of DATA_ROM_WORD;
    signal DATA_ROM : DATA_ROM_TABLE := DATA_ROM_TABLE'
    ( 
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000") --NOP
    );

begin

    process ( ADDR, CLK, WE ) is
    begin
        if ADDR <= X"FF" and CLK = '1'
        then
            EN <= '1';
            D_OUT <= DATA_ROM(conv_integer(ADDR));
            if WE='1'
            then
                DATA_ROM(conv_integer(ADDR)) <= D_IN;
            end if;
            EN <= '0';
        end if;
    end process;

end rom_arch;

Upvotes: 0

Views: 56

Answers (1)

DarkestSoul1992
DarkestSoul1992

Reputation: 9

Missing semi-colon before end. Always check that punctuation. 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ROM is
port (
    ADDR : in std_logic_vector (31 downto 0);
    D_IN : in std_logic_vector (63 downto 0);
    D_OUT : out std_logic_vector (63 downto 0);
    CLK : in std_logic;
    WE : in std_logic;
    EN : out std_logic
);
end ROM;

architecture rom_arch of ROM is

    constant INVALID_DATA : std_logic_vector (63 downto 0) := (others => 'X');
    subtype DATA_ROM_WORD is std_logic_vector (63 downto 0);
    type DATA_ROM_TABLE is array (0 to (2**3)-1) of DATA_ROM_WORD;
    signal DATA_ROM : DATA_ROM_TABLE := DATA_ROM_TABLE'
    ( 
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000") --NOP
    );

begin

    process ( ADDR, CLK, WE ) is
    begin
        if ADDR <= X"FF" and CLK = '1'
        then
            EN <= '1';
            D_OUT <= DATA_ROM(conv_integer(ADDR));
            if WE='1'
            then
                DATA_ROM(conv_integer(ADDR)) <= D_IN;
            end if;
            EN <= '0';
        end if;
    end process;

end rom_arch;

Upvotes: 0

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