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Reputation: 11

VHDL using an output from an instantiated entity in my toplevel entity

I've a VHDL code with a top entity and several other entities. Now there is an output in one of the subentities of which the value has to be brought to the toplevel entity to show it in my simulation program. How can i do that?

TOP entity:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity multiplier is
    port( Clk   : in        std_logic; -- Clock
          A,B   : in        std_logic_vector(7 downto 0); -- A and B
          Start : in        std_logic; -- Start
          Y     : buffer    std_logic_vector(15 downto 0); -- Result of A * B
          Ready : out       std_logic); -- Ready
end multiplier;

architecture structural of multiplier is

-- declaration of signals between different sub-circuits inside the multiplier
signal smInit, smCheck, smAdd, smShift, smZero, smReady, Stop : std_logic;
signal SR_A, SR_B, ADDout, MUXout : std_logic_vector(15 downto 0);

begin
io01: Ready <= smReady;

-- Instantiation of the FSM controller
sm01: entity work.FSM port map( Start, Stop, SR_A(0), Clk,
smReady, smInit, smCheck, smAdd, smShift, smZero);

-- Instantiation of the other sub-circuits and their connections
    SR1: entity work.Shifter port map(smInit, smShift, '0', Clk, A, SR_A);
    SR2: entity work.Shifter port map(smInit, smShift, '1', Clk, B, SR_B);
    A1: entity work.Add16 port map(SR_B, Y, ADDout);
    M1: entity work.Mux16 port map(smAdd, ADDout, Y, MUXout);
    G1: entity work.Reg16 port map(smInit, Clk, MUXout, Y);
    Z1: entity work.AllZero port map(SR_A(7 downto 0), Stop);
end structural; -- end of the multiplier architecture`

Now in the following subentity there is output S which i need to be able to call in the toplevel entity:

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity Add16 is
port( A, B : in std_logic_vector(15 downto 0);
S : buffer std_logic_vector(15 downto 0));
end Add16;
architecture behavior of Add16 is
signal Addout : out std_logic_vector (15 downto 0);
begin
S <= A + B;
end behavior;

How do i do that?

Upvotes: 1

Views: 804

Answers (1)

Morten Zilmer
Morten Zilmer

Reputation: 15924

VHDL-2008 has a "external names" concept, whereby a hierarchical reference is possible, so you don't need to manually route internal signals through the hierarchy if the test bench needs access to the value.

If the top-level test bench name is tb and the multiplier instance name is multiplier_e then an alias for the S port on Add16 can be created in the test bench using:

alias S_tb is <<signal .tb.multiplier_e.A1.S : std_logic_vector(15 downto 0)>>;

Upvotes: 1

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