CODEWITHSUNDEEP
vhdl
Антон Козлов
Антон Козлов

Reputation: 1

Statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition(vhdl)

There is a code that should switch CHG_UP if the OVR and UND variables are switched.

entity switcher_for_diod is
    Port ( OVR : in  STD_LOGIC;
           UND : in  STD_LOGIC;
           CHG_UP : out  STD_LOGIC);
end switcher_for_diod;

architecture Behavioral of switcher_for_diod is

signal NEW_UP: STD_LOGIC := '1';

begin
    process (OVR, UND, NEW_UP)
    begin
        if OVR'event and OVR = '1' then
            NEW_UP <= '0';
        end if;
        if UND'event and UND = '1' then
            NEW_UP <= '1';
        end if;
    end process;
    
    CHG_UP <= NEW_UP;
    
end Behavioral;

The error occurs in the second if, but if I remove it, the error disappears. Please help me figure out how to make sure that there is no error with the second if.

Upvotes: -3

Views: 79

Answers (1)

Aaron Linnell
Aaron Linnell

Reputation: 152

Your synthesis tool sees NEW_UP being assigned on two clock edges. OVR and UND are inferred to be clocks by their usage, predicating an assignment to a signal. It's unlikely that the tool has a leaf cell that can satisfy this request. To see why, consider this similar description:

signal UP_TRIG : bit := '1';
signal DOWN_TRIG : bit := '0';
...
CHG_UP <= UP_TRIG xor DOWN_TRIG;
...
process (OVR, UND)
begin
    if OVR'event and OVR = '1' and CHG_UP = '1' then
        UP_TRIG <= not UP_TRIG;
    end if;

    if UND'event and UND = '1' and CHG_UP = '0' then
         DOWN_TRIG <= not DOWN_TRIG;
    end if;
end process;

This may be close to what you want: Whenever OVR rises, CHG_UP goes low if it wasn't already. Whenever UND goes high, CHG_UP goes high if it wasn't already. This is also synthesizable because each assigned signal is only edge sensitive to one clock.

However, this is not the same for the case where both OVR and UND go high at the same time. In your original code, the last assignment to NEW_UP must be reflected, so CHG_UP will be '1'. But in this modified code, toggling is always favored over holding the previous value of CHG_UP. Since your tool is unable to infer a way to do the request behavior, it isn't synthesizable. That said, its always possible for a tool to fail to synthesize something which might be synthesizable, but is an unusual pattern which the implementer did not account for.

Upvotes: 0

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