CODEWITHSUNDEEP
vhdlfpgasynthesize
John
John

Reputation: 63

Fixing statement not synthesizable since it does not hold its value under NOT(clock-edge) condition

--Signal declaration
architecture Behavioral of Traffic_Light_Change is
signal State_A: STD_LOGIC;
signal segmentA : STD_LOGIC_VECTOR (0 to 6);
signal segmentB : STD_LOGIC_VECTOR (0 to 6);
signal counter : integer range 0 to 50000000:= 0;
signal State_T: std_logic;
begin
-- Switching anodes
anode_switching: process (clk_in, segmentA, segmentB)
begin 
if(rising_edge(clk_in)) then */ Line 78 error */ 
    State_A <= '1'; 
elsif(falling_edge(clk_in)) then
    State_A <= '0';
end if;
end process anode_switching;

Hello I keep getting this error when I attempt to synthesize my code. "Line 78 statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition." What am I doing incorrectly here that causes this to occur?

Upvotes: 0

Views: 514

Answers (1)

Matthew
Matthew

Reputation: 13987

Synthesis is the process of turning HDL code into hardware. Your code cannot be turned into hardware, because State_A changes on both edges of the clock. How would you implement such behaviour in hardware?

See my answer here.

Upvotes: 0

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