CODEWITHSUNDEEP
system-verilogassertionsfrequency-analysissystem-verilog-assertions
wisemonkey
wisemonkey

Reputation: 571

How to avoid very last assertion (if I understood it properly)

I'm following http://verificationguild.com/modules.php?name=Forums&file=viewtopic&p=5019 to check period of particular signal. That method works perfectly, but at very end of simulation if assertion is kicked by posedge (active edge) it basically fails cause there is no next edge.

Please consider following example: testbench clock is running at 2MHz, update clock (on which I've assertion written) is running at 5Hz (period 200ms) for particular test. Lets say simulation is running for 500ms of time, Assertion kicked at time 400ms fails.

How should I avoid this situation?

Upvotes: 1

Views: 1526

Answers (1)

nguthrie
nguthrie

Reputation: 2685

You need to disable the assert_report_incompletes variable. Create a file called irun_variables.tcl that contains:

set assert_report_incompletes 0
run

Then start irun with the -input irun_variables.tcl option. This will make it so incomplete assertions are not marked as failures.

Upvotes: 1

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