CODEWITHSUNDEEP
makefiledependencies
dbn
dbn

Reputation: 13920

How to remove dependency definitions from a Make target?

I'm working on a large project (~3x10^6 lines of code) that builds with nested Makefiles. I have a file (subdirs.mk) which adds some convenience rules for operating on all subdirectories (possibly in parallel). It includes these rules:

$(SUBDIRS_INCLUDES):
$(MAKE) -C $(patsubst %-includes,%,$@) includes

SUBDIRS_INCLUDES := $(patsubst %,%-includes,$(SUBDIRS))

includes: $(SUBDIRS_INCLUDES)

It also provides similar rules for install, clean, test, etc.

In one of my upper level Makefiles, I have this code:

SUBDIRS = dir1 dir2 dir3
include $(BUILD_TOOLS)/subdirs.mk

includes: $(BUILD_DIR)/version.h

I would like the includes target in this one case to only make $(BUILD_DIR)/version.h, skipping running includes in all the sub-directories. However, I still want to use subdirs.mk, because it provides other useful functions (the aforementioned test and install targets).

Is there a way to clear the dependencies from the includes target?

Upvotes: 1

Views: 1819

Answers (2)

radical7
radical7

Reputation: 9114

Irix, the Unix variant from Silicon Graphics (SGI), solved this problem by providing a variable in the equivalent of your subdirs.mk file that prefaced all of the included rules. You then set this prefix in all the children makefiles before you include subdirs.mk.

While it's a lot to absorb, these files: commondefs, and commonrules provide the solution you're looking for.

Upvotes: 0

Phil Miller
Phil Miller

Reputation: 38118

Use a different name besides includes for one of the two targets. Make has no notion of 'subtracting' or 'removing' dependencies.

Upvotes: 3

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