Reputation: 131
I'm exploring a feature of some software that's used in a very mature Makefile to see if that feature can be incorporated into the flow. There is a target like the following:
my_target: dependency_1 dependency_2
echo foo
touch bar
# etc...
In regular use, dependency_2 would always be called before my_target's commands were executed. But for my exploration purposes, I want to selectively call dependency_2 from its own make command. And then make my_target after, possibly several times, without re-doing dependency_2 each time.
For the time being I just copy/pasted my_target into my_target_2 and removed the dependency from my_target_2 (easy enough), but I'm wondering if there's a command-line option to disable a target's dependency without modifying the file.
EDIT: dependency_2 is a PHONY target
Upvotes: 1
Views: 768
Reputation: 100836
There's no way to do this without editing the makefile, that I can think of.
You can put dependency_2
into a variable then use the variable in the prerequisite list of my_target
:
dependency_2 = dependency_2
my_target : dependency_1 $(dependency_2)
then when you don't want to rebuild it, run make dependency_2=
to reset the variable to empty.
Upvotes: 1
Reputation: 15091
But for my exploration purposes, I want to selectively call dependency_2 from its own make command
This is done as easy as make dependency_2
And then make my_target after, possibly several times, without re-doing dependency_2 each time
Normally, dependency_2 should be a file on the disk, so make would skip rebuilding it until its own prerequisites (source files) are changed.
But if dependency_2 is a .PHONY target ("fake file"), it will be rebuilt on each run. In this case you still can fool it like this:
echo "dependency_2:;@:" | make -f Makefile -f -
However, make will issue a warning about overriding a recipe for dependency_2.
Upvotes: 2