CODEWITHSUNDEEP
system-verilog
Rich
Rich

Reputation: 1185

SystemVerilog vs C++ assignment: reference or copy?

I have primarily a C++ background. I was tracking down a bug in some SystemVerilog code I am working on and was surprised to find what I thought was an object-copying assignment was actually a reference assignment. This simplified code shows what I mean:

for (int i = 0; i < max_num; ++i)
{
    var cls_obj obj1;
    obj1 = obj_array[i];

    some_function(obj1); // modifies the object passed in

    // at this point BOTH obj1 and obj_array[i] are modified.

    // some other code goes here
}

I was expecting only obj1 to be modified. Is this because of the var keyword? How exactly does copy assignment vs. reference assignment work in SystemVerilog? I am having a hard time finding information from web searches.

Upvotes: 5

Views: 4405

Answers (2)

Lincoln Yesire
Lincoln Yesire

Reputation: 309

I also note this problem when i learn C++ and then SV.Actually, all sv propertys are depicted in detail in the LRM(The latest version is IEEE-1800-2017).This problem is stated in chapter 8.2 and chapter 13.5:

in chapter 13.5: about the subroutine

SystemVerilog provides two means for passing arguments to tasks and functions: by value and by reference. Arguments can also be bound by name as well as by position. Subroutine arguments can also be given default values, allowing the call to the subroutine to not pass arguments

in conlusion:
subroutine(include function and task) parameter pass by value by default, and pass by reference only if you add ref keyword.

chapter 8.2： about the class and object

The object-oriented class extension allows objects to be created and destroyed dynamically. Class instances, or objects, can be passed around via object handles, which provides a safe-pointer capability. An object can be declared as an argument with direction input, output, inout, or ref. In each case, the argument copied is the object handle, not the contents of the object.

In conclusion:
object is instance of class, the name of object is its reference or handle, not itself, which similar to pointer(declare by type *ptrname) or reference(delcare by: type &refname) in c++.So whenever, you mamipulate the object, you manipulate its handle. Therefore, when you pass the object to a subroutine without ref keyword althrough, it will pass by value, but the value(object name) is the handle of the object, not the object itself.As a result, class is passed by reference wether you add ref keyword or not.

In addition, this is why for new commers in SV , there comes a very common error as flowing(Comes from SystemVerilog for Verification, Second Edition: A Guide to Learning the Testbench Language FeaturesJune 2008):

> task generate_transaction()
Transaction t;
mailbox mbx;
**t = new(); // wrong place**
repeat(10) begin
    assert(t.randomize());
    mbx.put(t);
end

The bug is: only create one instace of class Transaction, so in the mailbox mbx the 10 object point to the single identical instance. The right way is creating many object in whenever you want the object, in other words, put the "t = new()" in the loop block.

> task generate_transaction()
Transaction t;
mailbox mbx;
repeat(10) begin
    **t = new(); // right place**
    assert(t.randomize());
    mbx.put(t);
end

Upvotes: 0

dwikle
dwikle

Reputation: 6978

Class variables in SystemVerilog are references, or handles. Instances are only created when you use the new keyword.

So in your example, obj1 and obj_array[i] both refer (or point) to the same instance.

By default, function parameters in SystemVerilog are passed by value. However class handles are treated as values, so any class you pass into a function is effectively passed by reference.

There is a built-in mechanism in the language to do a shallow copy when initializing a class object.

Packet p1;
Packet p2;
p1 = new;
p2 = new p1;

This does a shallow copy. For objects only the handles are copied!

This is explained with examples in Chapter 8.11 of IEEE 1800-2009.

The var keyword does not have anything to do with the behavior you are seeing. In fact, I've never even seen or used var. According to the LRM this allows one to omit the type when declaring the variable. In you code, the type (cls_obj) is specified so I don't think its presence is doing any thing.

Upvotes: 6

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