Reputation: 729
I'm trying to convert my program to use plugins and I'm having some trouble with the Makefile. I want the Makefile to look in the directory plugins, compile all the .c files found there with two different extensions .so and .o, preferably into a separate folder. Basically the same as this:
gcc -shared -lc -o testPugin.so testPugin.o
gcc -c -fpic testPugin.c
gcc Cprogram.c -ldl
But for an indeterminate number of .c files.
So far I've managed to look into the plugin directory and find all the files, but I'm stuck on compiling them according to the second step above and outputting the .so and .o files. Here is what I have so far:
TOP := $(dir $(lastword $(CURDIR)))
PLUGDIR = $(TOP)src/plugins
PLUGSRC = $(PLUGDIR)/*.c
OBJ = $(PLUGSRC:.c=.o)
SRCS = Cprogram.c
CFLAGS = -shared -lc
BINARY = testProg
$(BINARY): $(SRCS)
echo $(OBJ)
But that just outputs:
⇒ make
echo /Users/fragmachine/eclipse-workspace/Cprogram/src/plugins/*.o
/Users/fragmachine/eclipse-workspace/Cprogram/src/plugins/*.o
If I change OBJ = $(PLUGSRC:.c=.o)
to OBJ = $(SRCS:.c=.o)
I get:
⇒ make
echo Cprogram.o
Cprogram.o
Which is sort of what I want but it's only for one file. I think I must be missing a wildcard character of some sort but I've tried using % and * with no luck.
In case it isn't clear what I'm trying to do, here is some strange make pseudo code:
$(BINARY): $(SRCS)
gcc -shared -lc $(All plugin.c files) -o $(OBJ) #Output .o files for each plugin.c file
gcc -shared -lc $(All plugin.c files) -o $(OBJ2) #Output .so files for each plugin.c file
gcc -c -fpic $(All plugin.c files) # I'm not 100% sure what this does
gcc Cprogram.c -ldl # Compile the main program
I don't have much experience with make
at all. I've only made really simple ones before so any help would be greatly appreciated.
Upvotes: 1
Views: 2008
Reputation: 2720
Here is something to get you started:
PLUGDIR = src/plugins
PLUGSRC = $(PLUGDIR)/*.c
SRCS = $(wildcard $(PLUGSRC))
OBJ = $(SRCS:.c=.o)
SOBJ = $(SRCS:.c=.so)
CFLAGS = -shared -lc
BINARY = testProg
all: $(BINARY)
@echo "make is fun!"
$(BINARY): $(OBJ) $(SOBJ)
@echo "build the binary $@ which depends on $^"
%.o: $(SRCS)
@echo $@
%.so: $(SRCS)
@echo $@
First, this uses the $(wildcard) function to collect all *.c names in the src/plugins directory.
Second this uses a target all which depends on all of the .o files and .so files.
Third there are two pattern rules to build a .so and a .o file from a .c file.
Fourth your path to the source used $(TOP)src/plugins, but you are building in $(TOP) so that isn't the right relative path... you just want src/plugins.
So when you run this make the output is (assuming there is a file called src/plugins/Cprogram.c):
$ make
src/plugins/Cprogram.o
src/plugins/Cprogram.so
build the binary testProg which depends on src/plugins/Cprogram.o src/plugins/Cprogram.so
make is fun!
Hopefully from this you should be able to figure the rest out.
For more see my project template: https://github.com/cdesjardins/makefiles
Any time I am starting a new project I use that repo as a starting point.
Upvotes: 1