Is there any way to create a high level language interpreter implemented in hardware?

Question

Some random thoughts caught me and I just cannot get it out. I am thinking since morden processors are just interpreters for different kinds of assembly languages, is there anyway to create some high-level language interpreters directly implemented in hardware, using some HDLs or even directly designed using logic gates? Meanwhile I am thinking why this is not done yet, some reasons that I can think of now are:

• Theoretical reasons -- It is theoretically impossible, though in my opinion it is possible since either cpus we already have or the machine we are talking about is just a variant of Turing machine so there is no difference in their natures, but I am not 100% sure about this.
• Design complexity -- It's generally too difficult to create such a complex machine.
• Speed drawbacks -- Even it is properly designed and implemented, it still cannot win because their speed will be a disadvantage of it.

I am just generally curious about this problem.

Answer 1

Burroughs famously had "Algol in hardware" (see B5500).

Less known is Burroughs beautiful B1700, which let each process define microcode to interpret the HLL that the process code used. So, each process could have a different HLL instruction set; the hardware switched microcode sets on a context switch.

A lesson from the RISC world is that is more economical (and you get a larger market) to build a conventional instruction set, and compile the code for your language down to those instructions. The DEC VAX tried to have language-specific instructions; it turned out to be faster to use the more conventional VAX instructions instead of the specific ones.

If you insist, it is probably relatively easy to implement a HLL instruction set using an FPGA. (I can imagine this being a graduate student project in an EE design class). It just won't be performance competitive with an x86 or other modern RISC chip.

Answer 2

Ever heard of LISP machines or the company Symbolics.

I know the answers is short and is mostly links, but the answer is self contained.

Answer 3

This has already been done The Java processor.

Would this not be a very complex instruction set computer (VCISC) which leads to physically large processors. Some parts of the language are not used as often as others, this results in rarely used sections of processor, wasted silicon area.

Bigger die sizes for the processor increaes yield loss which increases the price for the end user. The economics of this favour smaller simple processors.

Low power processor designs are tending to favour RISC over CISC architectures. Super computers such as Deep Blue used many RISC cores. Most mobile communication devices use ARM RISC cores.