Reputation: 33
I have three files written in C:
a.c, b.c, d.c
I want to use ONE Makefile to generate independent executable files from them, like this:
a.x, b.x d.x.
They don't need each other to run. They are completely different programs.
I know, I can write a line to compile each one of them, like this:
gcc -Wall -Werror a.c -o a.x
gcc -Wall -Werror b.c -o b.x
gcc -Wall -Werror d.c -o d.x
But I am searching for an easier solution to do this independently from the number of files, due to the fact, that in the future I am going to have a lot of them.
I have an original that looks like this:
CC = gcc
CFLAGS = -g -Wall - Werror -03
%.x:%.c
${CC} {CFLAGS} -o $@ $<
clean:
rm -f *.o
But I don't know, how to customize it, so that it read each one of my c-files and generate a x-file from each one of them.
Thanks
Upvotes: 3
Views: 891
Reputation: 16406
Have you tried adding
all: a.x b.x c.x
in front of your makefile?
all: a.x b.x c.x
CC = gcc
CFLAGS = -g -Wall - Werror -03
%.x:%.c
${CC} {CFLAGS} -o $@ $<
clean:
rm -f *.o
Edit: To build all the .c files in the directory, try
all: $(*.c:.c=.x)
I'm quite rusty on Make so this might not quite be right ... You should read the Make documentation.
Edit 2: Indeed that wasn't right ... this is more likely to work:
SRCS = *.c
all: $(SRCS:.c=.x)
Or
SRCS = *.c
PGMS = $(SRCS:.c=.x)
all: $PGMS
Upvotes: 5