CODEWITHSUNDEEP
vhdl
Sunny Kumar
Sunny Kumar

Reputation: 11

Run multiple processes in VHDL

I am trying to simulate a microprocessor in VHDL as part of an assignment. Its a very basic model and doesn't even need to include all the opcodes. I would like to get around the following problem.

I have to run mr_process after mw_process. However, only mw_process runs infinitely, as seen in wave diagram. 

BEGIN
m : CODEMEM PORT MAP(addbus, data_in, data_out, control);

mw_process : process -- Write the entered commands

begin
  addbus <= "00000000"; -- mvi a, 0f
  data_in <= "00001111";
  control <= '1';
  wait for 100 ps;
  addbus <= "00000001";
  data_in <= "00001111";
  control <= '1';
  wait for 100 ps;
  addbus <= "00000010"; -- mvi b,08
  data_in <= "00001000";
  control <= '1';
  wait for 100 ps;
  addbus <= "00000011";
  data_in <= "00001000";
  control <= '1';
  wait for 100 ps;      

end process;

mr_process : process -- Read the entered commands

begin
  addbus <= "00000000"; -- mvi a, 0f
  control <= '0';
  wait for 100 ps;      
  addbus <= "00000001";
  control <= '0';
  wait for 100 ps;
  a <= data_out;

  addbus <= "00000010"; -- mvi b,08
  control <= '0';
  wait for 100 ps;
  addbus <= "00000011";
  control <= '0';
  wait for 100 ps;      
  b <= data_out;

end process;

L1:  ALU PORT MAP(A, B, '1', "001", RES, CARRY, ZERO);

Please help me out with this problem.

Upvotes: 1

Views: 4767

Answers (2)

user1818839
user1818839

Reputation:

The real problem here is that both processes are writing to the same control signal and address bus, at approximately the same time, so that one process wins. You could see both processes running if you offset one by 50ps at its start, but that won't solve the real problem.

You need some means of allowing both processes to share these signals. For example, by giving the reader and writer their own control and address signals, and combining them in a third process (called an arbiter) that arbitrates between them to allow them to take turns accessing the memory.

It is also normal to use a clock to synchronise these processes and use "wait until rising_edge(clk)" instead of lots of custom delays which are easy to get wrong.

A clock signal generator can be as simple as clk <= not clk after 50 ps; then if you want to change the speed, you only have one number to change instead of 8 (so far!)

Upvotes: 1

Martin Thompson
Martin Thompson

Reputation: 16832

Processes always run infinitely unles you tell them to stop.

Add a wait; to make them stop when you want them to.

Upvotes: 1

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